List of Messages |
CAUSE: The specified WYSIWYG RAM primitive has the ECC_PIPELINE_STAGE_ENABLED parameter set to TRUE. This setting is supported only if the WYSIWYG RAM primitive makes use of its output registers.
ACTION: Modify your design to use the output registers or set the ECC_PIPELINE_STAGE_ENABLED parameter to FALSE on the specified WYSIWYG RAM primitive.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.