List of Messages |
CAUSE: The specified WYSIWYG RAM primitive is using ECC and mixed-port read-during-write mode at the same time. This is not allowed.
ACTION: Check your design and make sure you don't use the ECC feature and old memory content mixed-port read-during-write mode at the same time.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.