List of Messages |
CAUSE: The specified WYSIWYG MCELL primitive is in register mode (that is, the OUTPUT_MODE parameter is set to REG), DFF mode (that is, the REGISTER_MODE parameter is set to DFF) and VCC mode (that is, the OPERATION_MODE parameter is set to VCC), but does not use the fpin fast input port. The fpin port must be used when the WYSIWYG primitive is in register mode, DFF mode, and VCC mode.
ACTION: If you are using an EDA tool, contact the technical support for the EDA tool regarding this message. For further assistance, contact Altera Technical Support by creating a Service Request at www.altera.com/mysupport.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.