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CAUSE: This message contains submessages. For the names of the affected I/O cells and the partitions to which they belong, refer to the submessages. One or more design partitions contain non-trivial I/O cells that either do not connect to top-level pins directly, or have illegal connectivity. An I/O cell can have only a single wire connection to a top-level device I/O pin. If you are using design partitions exported from another Quartus Prime project, this error can occur for non-trivial I/O cells generated in a lower-level project. If you compile all your partitions in the top-level project, this error may occur because of WYSIWYG I/O atoms in your HDL files.Another possible reason for the error to occur when using incremental compilation is when you use tristate logic in lower-level partitions, which will be implemented as an I/O atom.
ACTION: When performing incremental compilation in a Quartus Prime project, you can restructure your HDL, partition assignments, or both, to ensure that any tristate logic and dedicated I/O instantiated in lower-level partitions connect directly to top-level pins. For exported partitions, you can make Virtual Pin assignments in the lower-level project for all the affected pins.
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