Performing a Timing Simulation with the ModelSim-Altera Software
Parent topic: Performing a Timing Simulation with the ModelSim-Altera Software Previous topic: To perform a timing simulation of a ModelSim project with the ModelSim-Altera interface Next topic: Performing a Functional Simulation with the Incisive Enterprise Simulator Software

To perform a timing simulation of a ModelSim project with command-line commands

Note: Note: You can use batch files to set up and compile each of the libraries automatically. Place all the commands displayed in the ModelSim-Altera or ModelSim PE or SE main window into a text file and name the file with a .do extension (that is,<file name>.do). Use this script to recompile the libraries if you update them.

To run a macro script:

  1. From the Mentor Graphics ModelSim main window, choose Execute Macro.
  2. In the Execute Do File dialog box, locate your ModelSim macro file (.do).
  3. Click Open.
  1. If you have not already done so, map to libraries and compile design files with the ModelSim-Altera software.
  2. If your design contains device-wide reset or device power up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.
  3. Type the following commands at the ModelSim prompt to load the design with minimum, typical, or maximum timing values.
    For VHDL designs:

    vsim -t ps-sdf(min | typ | max) +transport_int_delays +transport_path_delays /=<design name> .sdo work.<top-level design entity>

    For Verilog HDL designs:

    vsim -t ps +transport_int_delays +transport_path_delays -L<device family>_ver -sdf(min | typ | max)work. <top-level design entity>

  4. To direct the ModelSim-Altera software to generate a Value Change Dump File (.vcd) Definition that you can then use to perform power analysis in the Quartus® Prime Standard Edition PowerPlay Power Analyzer, type the following command at the ModelSim prompt:
    source<testbench or design instance name>_dump_all_vcd_nodes.tcl

    The Tcl Script File directs the ModelSim-Altera software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.

  5. Perform the timing simulation in the ModelSim-Altera software.
    Note: Note: Refer to the ModelSim software documentation to view and interpret the results of your simulation.
Related information

Mappin to Llibraries and Compiling Design Files with the ModelSim-Altera Software
Setting Up Device-Wide Signals in Verilog HDL
sSetting Up Device-Wide Signals in VHDL
Parent topic: Performing a Timing Simulation with the ModelSim-Altera Software Previous topic: To perform a timing simulation of a ModelSim project with the ModelSim-Altera interface Next topic: Performing a Functional Simulation with the Incisive Enterprise Simulator Software

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