Performing a Timing Simulation with the ModelSim-Altera Software

You can perform a timing simulation of a Verilog HDL, SystemVerilog HDL, or VHDL design with the Mentor Graphics ModelSim-Altera software from the ModelSim-Altera interface or with command-line commands.

Important: Altera recommends that you set Time scale settings to picoseconds (ps) in the interface or with command-line commands when performing timing simulation.
Note: For more information about using EDA simulators, refer to Mentor Graphics ModelSim and QuestaSim Support in the Quartus® Prime Standard Edition Handbook.
If you want to perform power analysis, proceed to perform power analysis with the PowerPlay Power Analyzer.