Performing a Simulation of a VHDL Design with the Active-HDL Software
Parent topic: Performing a Simulation of a VHDL Design with the Active-HDL Software Previous topic: Performing a Simulation of a VHDL Design with the Active-HDL Software Next topic: Perform a Post-Synthesis Simulation

Perform an RTL Functional Simulation

  1. To verify that pre-existing libraries are not attached in the Active-HDL software:
    1. On the View menu, click Library Manager. The Library Manager window appears.
    2. Browse to <Active-HDL installation directory>/vlib/altera_mf.
    3. If simulation libraries are present for your version of the Quartus® Prime Standard Editionsoftware, you can skip to step 5. Otherwise, you can download the appropriate library files from the Aldec website or create them manually with steps 2 through 4.
  2. To create a workspace and compile simulation libraries in the Active-HDL software:
    1. On the File menu, point to New and click Design. The New Design Wizard appears.
    2. Select Create an Empty Design and keep the Create New Workspace option selected.
    3. Click Next. The Property page appears. In the Property page, click Next.
    4. Type the name in the Design name and Library name fields, for example, altera_mf or lpm. Select the location of your design in the Design folder field, and click Next. Altera recommends that you use same name for the design and the library.
    5. Click Finish to complete the wizard.
    6. On the Design menu, click Add files to Design.
    7. Browse to <Quartus® Prime Standard Edition installation directory>/eda/sim_lib and add the necessary simulation model files. For example, compile the altera_mf.vhd model files into the altera_mf library, and compile the 220model.vhd model files into the lpm library.
    8. On the Design menu, click Compile All to compile all the files and add them to the design library, for example, altera_mf_components.vhd and altera_mf.vhd.
    9. On the File menu, click Close Workspace.
  3. You must map the created library in the Active-HDL software. To map simulation libraries:
    1. On the View menu, click Library Manager. The Library Manager window appears.
    2. On the Library menu, click Attach Library.
    3. Locate the .lib file, for example, altera_mf.lib or lpm.lib, from the design directory that you created in the previous steps and click Open.
  4. To create a workspace in the Active-HDL software and compile your testbench and design files into the work library:
    1. On the File menu, point to New and click Design. The New Design Wizard appears.
    2. Select Create an Empty Design and keep the Create New Workspace option selected.
    3. Click Next. The Property page appears. In the Property page, click Next to proceed to the Design name and Library name fields.
    4. Type work for the design name and select the location of your design. Altera recommends that you use the same name for your the design and the library.
    5. Click Finish to complete the wizard.
    6. On the Design menu, click Add files to Design.
    7. Browse to the RTL design directory and add the testbench and RTL design files.
    8. On the Design menu, click Compile All to compile the testbench and RTL design files.
    Important: Resolve compile-time errors before proceeding to the following steps.
  5. To add your testbench files in the Active-HDL software, in the Design Browser, click the Top-level Selection list. Select the top-level module, which is your testbench with corresponding architecture.
  6. In the Design Settings dialog box, expand the Simulation category and click Access to Design Objects. Turn on Read (+r) to view waveforms in the Waveform window.
  7. To initialize simulation in the Active-HDL software, on the Simulation menu, click Initialize Simulation. This loads the simulation. The Design Browser automatically switches to the Structure tab and displays the design tree.
  8. To perform the simulation in the Active-HDL software:
    1. On the File menu, point to New and click Waveform.
    2. Drag signals of interest from the Structure tab of the Design Browser to the Waveform window.
    3. On the Simulation menu, click Run Until.
    4. In the pop-up window, specify how long you want your simulation to run, for example, 500 ns.
Parent topic: Performing a Simulation of a VHDL Design with the Active-HDL Software Previous topic: Performing a Simulation of a VHDL Design with the Active-HDL Software Next topic: Perform a Post-Synthesis Simulation

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