Setting Up the EDA Tool Environment

The Quartus^® Prime Standard Edition software supports integration with industry standard synthesis, simulation, and verification EDA tools. You must correctly install and setup the working environment for EDA software before using with Altera designs. You can use the Quartus^® Prime Standard Edition NativeLink feature to help you setup and integrate EDA tools into the Quartus^® Prime Standard Edition design flow, or you can use a custom flow if you require greater control.

To setup the EDA tool environment, follow these steps:

Install your supported EDA tool and setup your license path and other environment variables according to the EDA tool documentation.
If you have not already done so, create a new project or open an existing project.
On the Tools menu, click Options and then click EDA Tool Options. Specify the executable path of your EDA tool.
On the Assignments menu, click Settings.
To specify design entry or synthesis EDA tool settings, follow these steps:
1. In the Category list, click Design Entry/Synthesis under EDA Tool Settings.
2. In the Tool name list, select the name of design entry or synthesis tool, or select Custom.
3. In the Data Format box, enter the type of input file you are importing into the Quartus^® Prime Standard Edition software, which may include EDIF, Verilog HDL, VHDL, and AHDL, depending on the type of tool selected.
4. If you selected EDIF in the Data Format list, you can specify non-default VCC or GND signal names. If you want to change these names, type the new names in the VCC and GND boxes under Signal names. Entering non-default signal names changes the settings in the Tool name list to Custom.
5. To use a non-default Library Mapping File (.lmf) Definition, under Library Mapping File, type the file name in the File name box, or browse to that location.
6. To display messages about Library Mapping Files mapping during compilation, turn on Show information messages describing LMF mapping during compilation.
7. To automatically use the EDA tool during Quartus^® Prime Standard Edition Analysis and Synthesis, turn on Run this tool automatically to synthesize the current design.
Specify simulation EDA tool settings.
To specify board-level verification EDA tool settings, follow these steps:
1. In the Category list, click Board-Level under EDA Tool Settings.
2. Select the Format and Output directory for the type of board-level verification tool you plan to use: symbol generation, signal integrity, or timing analysis.
3. You can select Stamp (board model) in the Tool name list to perform timing verification on a board-level design and create the Stamp model files.
To specify formal verification EDA tool settings follow these steps:
1. In the Category list, click Formal verification under EDA Tool Settings.
2. Under Tool settings, in the Tool name list, select the name of the formal verification tool.
Click OK.

Note: Some Altera IP cores require a Quartus Prime Standard Edition IP File (.qip) Definition for synthesis or a Quartus Prime Standard Edition Simulation IP File (.sip) Definition for automated EDA tool simulation. Add these files to the project when generated for your IP core.