Advanced Fitter Settings Dialog Box

ALM Register Packing Effort

Guides aggressiveness of the Fitter in packing ALMs during register placement. Use this option to increase secondary register locations. Increasing ALM packing density may lower the number of ALMs needed to fit the design, but it may also reduce routing flexibility and timing performance.

• Low—The Fitter will avoid ALM packing configurations that combine LUTs and registers which have no direct connectivity. Avoiding these configurations may improve timing performance but will increase the number of ALMs used to implement the design.
• Medium—The Fitter allows some configurations that combine unconnected LUTs and registers to be implemented in ALM locations. The Fitter will make more usage of secondary register locations within the ALM.>
• High—The Fitter enables all legal and desired ALM packing configurations. In dense designs, the Fitter will automatically increase the ALM register packing effort as required to enable the design to fit.

Advanced Physical Optimization

Enables Advanced Physical Optimization to improve the quality of results with more consistent timing closure.

Allow Delay Chains

Allows the Fitter to choose the optimal delay chain to meet tSU and tCO timing requirements for all I/O elements. Turning on this option may reduce the number of tSU violations while introducing a minimal number of tH violations. Turning on this option does not override delay chain settings on individual nodes.

Allow Delay Chains for High Fanout Pins

Allows the Fitter to choose how to optimize the delay chains for high fanout input pins. You must enable Auto Delay Chains to enable this option. Enabling this option may reduce the number of tSU violation, but the compile time increases significantly, as the Fitter tries to optimize the settings for all fanouts.

Allow Single-ended Buffer for Differential-XSTL Input

Allows the pin with a Differential-XSTL IO-standard to be used with a single-ended input buffer.

Auto Fit Effort Desired Slack Margin

Specifies the default worst-case slack margin the Fitter maintains forAuto Fit for Fitter Effort. If the design is likely to have at least this much slack on every path, the fitter will reduce optimization effort to reduce compilation time. Otherwise, its behavior will be the same as it is with the Standard Fit setting.

Auto Global Clock

Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clock signal that is made available throughout the device on the global routing paths. If you want to prevent the Compiler from automatically selecting a particular signal as global clock, set the Global Signal option to Off on that signal.

Auto Global Register Control Signals

Allows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excluding clock signals) as global signals that are made available throughout the device on the global routing paths. Depending on the target device family, these control signals can include asynchronous clear and load, synchronous clear and load, clock enable, and preset signals. If you want to prevent the Compiler from automatically selecting a particular signal as global register control signal, set the Global Signal option to Off on that signal.

Auto Merge PLLs

Allows the Compiler to automatically find and merge together two compatible phase-locked loops (PLL) driven by the same clock source, reducing the total number of PLLs in a design.

Auto Packed Registers

Allows the Compiler to combine a register and a combinational function, or to implement registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells. This option controls how aggressively the Fitter combines registers with other function blocks to reduce the area of the design. Generally, the Auto or Sparse Auto settings are appropriate. The other options limit the flexibility of the Fitter to combine registers with other function blocks and can result in no fits. When Auto, the Fitter attempts to achieve the best performance with good area. If necessary, additional logic is combined to reduce the area of the design so that it can fit within the selected device. When this setting is Sparse Auto, the Fitter attempts to achieve the highest performance with possibly increased area, but without exceeding the logic capacity of the device. If this option is set to Off, the Fitter does not combine registers with other functions. The Off setting severely increases the area of the design and may cause a no fit. If this option is set to Sparse, the Fitter combines functions in a way which improves performance for many designs. If this option is set to Normal, the Fitter combines functions that are expected to maximize design performance and reduce area. When this option is set to Minimize Area, the Fitter aggressively combines unrelated functions to reduce the area required for placing the design, at the expense of performance. When this option is set to Minimize Area with Chains, the Fitter even more aggressively combines functions that are part of register cascade chains or can be converted to register cascade chains. If this option is set to any value but Off, registers are combined with I/O cells to improve I/O timing (as long as the Optimize IOC Register Placement For Timing option allows it), and with DSP blocks and RAM blocks to reduce the area required for placing the design or to improve timing when possible.

Auto RAM to MLAB Conversion

Specifies whether the Fitter is able to convert RAMs to use LAB locations when those RAMs use Auto as the selected block type. If this option is changed to Off, then only MLAB cells in the design or RAM cells with a block type setting of MLAB use LAB locations to implement memory.

Auto Register Duplication

Allows the Fitter to automatically duplicate registers within a LAB containing empty logic cells. This option does not alter the functionality of the design. The Auto Register Duplication option is also ignored if you select OFF as the setting for the Logic Cell Insertion -- Logic Duplication logic option. Turning on this option can allow the Logic Cell Insertion -- Logic Duplication logic option to improve a design's routability, but can make formal verification of a design more difficult.

Clamping Diode

Turns on the Clamping Diode of a pin. The clamping diode can limit overshoot voltage for a pin in input operation. The clamping diode is turned on by default for 3.0-V PCI/PCI-X I/O standards. The clamping diode is turned off by default for 3.3-V LVTTL/LVCMOS I/O standards. This option is ignored if it is applied to anything other than a pin or a top-level design entity.

Enable Beneficial Skew Optimization

Allows the fitter to insert skew on globally routed clock signals to improve the performance of the design.

Enable Bus Hold Circuitry

Enables bus-hold circuitry during device operation. If this option is turned on, a pin retains its last logic level when it is not driven, and does not go to a high impedance logic level. Do not use this option at the same time as Weak Pull-Up Resistor option. This option is ignored if it is applied to anything other than a pin.

Equivalent RAM and MLAB Paused Read Capabilities

Specifies whether RAMs implemented in MLAB cells must have equivalent pause read capabilities as RAMs implemented in block RAM. Pausing a read is the ability to keep around the last read value when reading is disabled. Allowing differences in paused read capabilities provides the Fitter more flexibility in implementing RAMs using MLAB cells. If this option is set to Don't Care, the Fitter may convert RAMs to MLAB cells even if they won't have equivalent paused read capabilities to a block RAM implementation. The Fitter also outputs an information message about RAMs with different paused read capabilities. If this option is set to Care, the Fitter does not convert RAMs to MLAB cells unless they have the equivalent paused read capabilities to a block RAM implementation. To allow the fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to Don't Care.

Equivalent RAM and MLAB Power Up

Specifies whether RAMs implemented in MLAB cells must have equivalent power up conditions as RAMs implemented in block RAM. Power up conditions occur when the device is powered up or globally reset. Allowing non-equivalent power up conditions provides the Fitter more flexibility in implementing RAMs using MLAB cells. If this option is set to Auto, the Fitter may convert RAMs to MLAB cells even if they won't have equivalent power up conditions to a block RAM implementation. The Fitter also outputs a warning message about RAMs with non-equivalent power up conditions. If this option is set to Don't Care, the same behavior as Auto applies, but the message is an information message. If this option is set to Care, the Fitter does not convert RAMs to MLAB cells unless they have equivalent power up conditions to a block RAM implementation. To allow the fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to Auto or Don't Care.

Final Placement Optimizations

Specifies whether the Fitter performs final placement optimizations. Performing final placement optimizations may improve timing and routability, but may also require longer compilation time. You can use the default setting of Automatically with the Auto Fit Fitter effort level (also the default) to allow the Fitter decide whether these optimizations should run based on the routability and timing requirements of the design.

Fit Attempts to Skip

Specifies the quantity of place and route attempts that the Fitter skips. In subsequent fit attempts, the Fitter uses higher effort to improve design routability at the expense of longer compilation times. Use this setting to direct the Fitter to make a second or third fit attempt. This strategy can save time when multiple attempts are needed. This setting causes the same amount of additional effort to be applied but does not guarantee an identical result to what would be achieved if all fit attempts were performed. For some device families, the Fitter does not perform a third fit attempt automatically due to the long compilation time and possible timing quality degradation. However, a third fit attempt can still be forced to run by setting this value to 2.

Fitter Aggressive Routability Optimizations

Specifies whether the Fitter aggressively optimizes for routability. Performing aggressive routability optimizations may decrease design speed, but may also reduce routing wire usage and routing time. The default Automatically setting allows the Fitter decide whether to perform these optimizations based on the routability and timing requirements of the design.

Fitter Effort

Specifies the level of physical synthesis optimization you want the Quartus^® Prime Standard Edition software to use when increasing the performance of a design, using the following options:

• Auto—Auto Fit adjusts the fitter optimization effort to minimize compilation time, while still achieving the design timing requirements. Use the Auto Fit Effort Desired Slack Margin option to request that Auto Fit apply sufficient optimization effort to achieve additional timing margin.
• Fast—Fast Fit decreases optimization effort to reduce compilation time, which may degrade design performance.
• Standard—Standard Fit uses maximum effort regardless of the design's requirements, leading to higher compilation time and more margin on easier designs. For difficult designs, Auto Fit and Standard Fit both use maximum effort.

These options are available for supported device (Arria series, Cyclone series, MAXII, MAXV, and Stratix series) families. For supported device (CycloneIII, CycloneIV, StratixIII, StratixIV, and StratixV) families, the Effort level optimizations are performed during synthesis and place and route. The Quartus^® Prime Standard Editionsoftware does not perform physical synthesis on any node or entity for which you set the Never Allow setting in the Netlist Optimizations logic option.

The Physical Synthesis Netlist Optimizations Report provides information about the physical synthesis optimizations performed.

Fitter Initial Placement Seed

Specifies the seed for the current design. The value can be any non-negative integer value. By default, the Fitter uses a seed of 1.

The Fitter uses the seed as the initial placement configuration when attempting to optimize the design's timing requirements, including fmax Definition. Because each different seed value will result in a somewhat different fit, you can try several different seeds to attempt to obtain superior fitting results.

The seeds that lead to the best fits for a design may change if the design changes. Also, changing the seed may or may not result in a better fit; therefore, you should specify a seed only if the Fitter is not meeting timing requirements by a small amount.

This option is available for all Altera device families supported by the Quartus^® Prime Standard Edition software.

Force Fitter to Avoid Periphery Placement Warnings

Directs the Fitter to treat periphery placement warnings as errors. As a result, the Fitter attempts to find a placement for the design that corrects these warnings. If the Fitter cannot fit the design, an error message is displayed instead of the original warning message.

Generate GXB Reconfig MIF

Generates a GXB reconfig MIF file for each used GXB Transmitter and Receiver channel pair (Strati GX and Arria GX) or each ALTGX IP core instance (Stratix IV, Arria II GX and Cyclone IV GX). Reprogramming using this MIF file reconfigures the GXB channel.

I/O Placement Optimizations

Specifies whether the Fitter optimizes the location of I/Os without pin assignments. Performing I/O placement optimizations may improve I/O timing, fMAX, and fitting, but may also require longer compilation time.

Limit to One Fitting Attempt

Controls how many place and route attempts the Fitter executes. When this option is off (default), the Fitter tries a maximum of 2 or 3 placement and routing attempts, with each successive attempt increasing the placement effort and hence increasing compilation times. These additional attempts are used only if previous attempts failed to fit the design. Setting this option restricts the fitter to using only the first of these attempts.

Logic Cell Insertion

Allows the Fitter to automatically insert buffer logic cells between two nodes without altering the functionality of the design. Buffer logic cells are created from unused logic cells in the device. This option also allows the Fitter to duplicate a logic cell within a LAB when there are unused logic cells available in a LAB. Using this option can increase compilation time. The default setting of Auto allows these operations to run when 1) the design requires them to fit the design or 2) the performance of the design can be improved by this optimization with a nominal compilation time increase.

M144K Block Read Clock Duty Cycle Dependency

Specifies whether the M144K memory block read operations depend upon the read clock's duty cycle. When M144K memory blocks are driven by a read clock with a very narrow pulse, they can go into a locked, inactive state. Turning on this option allows the M144K memory blocks to operate dependent upon the read clock's duty cycle to prevent the memory blocks from going into to an inactive state; however, turning on this option may degrade the performance of the M144K blocks.

MLAB Add Timing Constraints for mixed-Port Feed-Through Mode Setting Don't Care

Specifies whether you want the TimeQuest Timing Analyzer to evaluate timing constraints between the write and the read operation of the MLAB memory block. Performing a write and read operation simultaneously at the same address might result in metastability because no timing constraints between those operations exist by default. Turning on this option introduces timing constraints between the write and read operation on the MLAB memory block and thereby avoids metastability issues; however, turning on this option degrades the performance of the MLAB memory blocks. If your design does not perform write and read operations simultaneously at the same address you do not need to set this option.

Maximum number of clocks of any type allowed

Specifies the maximum number of clocks of any type (for example, global clock, regional clock) that can be used by the design. A value of -1 means that the Fitter can use all the clocks supported by the device. You can also specifically limit global, periphery, and regional clocks.

Optimize Design for Metastability

This setting improves the reliability of the design by increasing its Mean Time Between Failures (MTBF). When this setting is enabled, the Fitter increases the output setup slacks of synchronizer registers in the design, which can exponentially increase the design MTBF. This option only applies when using TimeQuest for timing-driven compilation. Use the TimeQuest report_metastability command to review the synchronizers detected in your design and to produce MTBF estimates.

Optimize Hold Timing

Directs the Fitter to optimize hold time within a device to meet timing requirements and assignments. The following settings are available:

• I/O Paths and Minimum TPD Paths—Directs the Fitter to meet the following timing requirements and assignments:
• • th (clock hold time) Definition from I/O pins to registers.
  • Minimum tco (clock to output delay) Definition from registers to I/O pins.
  • Minimum tpd (pin-to-pin delay) Definition from I/O pins or registers to I/O pins or registers.
• All Paths—Directs the Fitter to meet the following timing requirements and assignments:
• • tH from I/O pins to registers.
  • Minimum tCO from registers to I/O pins.
  • Minimum tPD from I/O pins or registers to I/O pins or registers.

This option is available for all Altera device families supported by the Quartus^® Prime Standard Edition software. When you turn off theOptimize Timinglogic option, the Optimize hold timing option is not available.

Optimize IOC Register Placement for Timing

Specifies whether the Fitter optimizes I/O pin timing by automatically packing registers into I/Os to minimize I/O -> register and register -> I/O delays. When you select Normal , the Fitter opportunistically packs registers into I/Os that should improve I/O timing. When you enable Pack All I/O Registers, the Fitter aggressively packs any registers connected to input, output or output enable pins into I/Os, unless prevented by user constraints or other legality restrictions. By default, this option is set to Normal. This option requires enabling the Optimize Timing option.

Optimize Multi-Corner Timing

Directs the Fitter to consider all corner timing delays, including both fast-corner timing and slow-corner timing, during optimization to meet timing requirements at all process corners and operating conditions. By default, this option is on, and the Fitter optimizes designs considering multi-corner delays in addition to slow-corner delays, for example, from the fast-corner timing model, which is based on the fastest manufactured device, operating under high-voltage conditions. When this option is off, the Fitter optimizes designs considering only slow-corner delays from the slow-corner timing model (slowest manufactured device for a given speed grade, operating in low-voltage conditions). Turning this option on typically helps to create a design implementation that is more robust across process, temperature, and voltage variations.

This option is available for all Altera device families supported by the Quartus^® Prime Standard Edition software. When you turn off the Optimize Timinglogicoption, the Optimize multi-corner timing option is not available.

Optimize Timing

Specifies whether the Fitter optimizes to meet the maximum delay timing requirements (for example, clock cycle time). By default, this option is set to Normal compilation. Turning it off can help fit designs that have extremely high interconnect requirements and can also reduce compilation time, although at the expense of significant timing performance (since the Fitter ignores the design's timing requirements). If this option is off, other Fitter timing optimization options have no effect (such as Optimize Hold Timing).

Optimize Timing for ECOs

Controls whether the Fitter optimizes to meet the user's maximum delay timing requirements (e.g.. clock cycle time, tSU, tCO) during ECO compiles. By default, this option is set to off. Turning it on can improve timing performance at the cost of compilation time.

Perform Asynchronous Signal Pipelining

Specifies that Quartus^® Prime Standard Edition should perform automatic insertion of pipeline stages for asynchronous clear and asynchronous load signals during fitting to increase circuit performance. This option is useful for asynchronous signals that are failing recovery and removal timing because they feed registers using a high-speed clock.

Perform Automatic Asynchronous Signal Pipelining

Perform Clocking Topology Analysis During Routing

Directs the Fitter to perform an analysis of the design's clocking topology and adjust the optimization approach on paths with significant clock skew. Enabling this option may improve hold timing at the cost of increased compile time.

Perform Logic to Memory Mapping for Fitting

Specifies that the Fitter should perform physical synthesis optimizations on logic and registers, specifically allowing the mapping of logic and registers into unused memory blocks during fitting to achieve a fit.

Perform physical synthesis for combinational logic for Fitting

Directs the Quartus^® Prime Standard Edition software to increase performance by performing physical synthesis on combinational logic. Because this process does not change registers, the internal register names remain unchanged, but there is less performance improvement possible than when you turn on Perform register duplication or Perform register retiming. Turn on Perform physical synthesis for combinational logic if you want to do extensive simulation of internal circuit functionality or formal verification. This option is available for all Altera device families supported by the Quartus^® Prime Standard Edition software.

Perform Physical Synthesis for Combinational Logic for Performance

Specifies that Quartus should perform physical synthesis optimizations on combinational logic during synthesis and fitting to increase circuit performance.

Perform Register Duplication for Performance

Automatically duplicates registers when appropriate to reduce the delay of one fan-out path without degrading the delay of the other fan-out path.

Perform Register Retiming for Performance

Directs the Quartus^® Prime Standard Edition software to increase performance by using register retiming to perform physical synthesis on registers. Register retiming improves the delay of synchronous sequential circuits by moving registers across combinational logic. This option is available for all Altera device families supported by the Quartus^® Prime Standard Edition software.

Physical Synthesis Effort Level

Specifies the amount of effort, in terms of compile time, physical synthesis should use. Extra uses extra compile time to try to gain extra circuit performance. Fast uses less compile time but may reduce the performance gain that physical synthesis is able to achieve.

Placement Effort Multiplier

Specifies the relative time the Fitter spends in placement. The default value is 1.0 and legal values must be greater than 0. Specifying a floating-point number allows you to control the placement effort. A higher value increases CPU time but may improve placement quality. For example, a value of '4' increases fitting time by approximately 2 to 4 times but may increase quality.

PowerPlay Power Optimization During Fitting

Directs the Fitter to perform optimizations targeted at reducing the total power consumed by the supported device(ArriaIIGX, MAXII, and StratixIV)families.

The available settings for power-optimized fitting are:

• Off—Performs no power optimizations.
• Normal compilation—Performs power optimizations that are unlikely to adversely affect compilation time or design performance.
• Extra effort—Performs additional power optimizations that might affect design performance or result in longer compilation time.

Programmable Power Maximum High-Speed Fraction of Used LAB Tiles

Sets the upper limit on the fraction of the high-speed LAB tiles. Legal values must be between 0.0 and 1.0. The default value is 1.0. A value of 1.0 means that there is no restriction on the number of high-speed tiles, and the fitter uses the minimum number needed to meet the timing requirements of your design. Specifying a value lower than 1.0 might degrade timing quality, because some timing critical resources might be forced into low-power mode.

Regenerate Full Fit Reports During ECO Compiles

Controls whether the fitter report is regenerated during ECO compiles. By default, this option is set to off. Turning it on will regenerate the report at the cost of compilation time.

Router Effort Multiplier

Specifies the relative amount of time for the router to find a fitting solution. The default value is 1.0 and legal values must be greater than or equal to 0.25. Values higher than 1.0 may improve routing quality at the expense of run-time on difficult-to-route circuits. Values lower than 1.0 can reduce router run-time, but usually reduces routing quality slightly.

Router Timing Optimization Level

Controls how aggressively the router tries to meet timing requirements. Setting this option to Maximum can increase design speed slightly, at the cost of increased compile time. Setting this option to Minimum can reduce compile time, at the cost of slightly reduced design speed. The default value is Normal.

SSN Optimization

Specifies how aggressively the Fitter optimizes the design for simultaneous switching noise (SSN). If this option is set to Off, the Fitter does not perform any SSN optimizations. If this option is set to Normal compilation, the Fitter performs SSN optimizations which should not impact design performance. When this option is set to Extra effort, the Fitter performs aggressive SSN optimizations which may affect design performance.

Synchronizer Identification

Specifies how the TimeQuest Timing Analyzer identifies registers as being part of a synchronization register chain for metastability analysis. A synchronization register chain is a sequence of registers with the same clock with no fan-out in between, which is driven by a pin or logic from another clock domain.

If this option is set to Off, the TimeQuest Timing Analyzer does not identify the specified registers, or the registers within the specified entity, as synchronization registers. If the option is set to Auto, the TimeQuest Timing Analyzer identifies valid synchronization registers that are part of a chain with more than one register that contains no combinational logic. If this option is set to Forced if Asynchronous, the TimeQuest Timing Analyzer identifies synchronization register chains if the software detects an asynchronous signal transfer, even if there is combinational logic or only one register in the chain. If this option is set to Forced, then the specified register, or all registers within the specified entity, are identified as synchronizers. Only apply the Forced option to the entire design. Otherwise, all registers in the design identify as synchronizers. Registers that are identified as synchronizers are optimized for improved Mean Time Between Failure (MTBF) as long as Optimize Design for Metastability is enabled.

If a synchronization register chain is identified with the Forced or Forced if Asynchronous option, then the TimeQuest Timing Analyzer reports the metastability MTBF for the chain. MTBF is not reported for automatically-detected register chains; you can use the Auto setting to generate a report of possible synchronization chains in your design. If a synchronization register chain is identified with the Forced or Forced if Asynchronous option, then the TimeQuest Timing Analyzer reports the metastability MTBF for the chain when it meets the design timing requirements.

Treat Bidirectional Pin as Output Pin

Specifies that the bidirectional pin should be treated as an output pin, meaning that the input path feeds back from the output path.

Weak Pull-Up Resistor

Enables the weak pull-up resistor when the device is operating in user mode. This option pulls a high-impedance bus signal to VCC. Do not enable this option simultaneously with the Enable Bus-Hold Circuitry option. This option is ignored if it is applied to anything other than a pin.