• Create simulation model—Creates a Verilog or VHDL simulation model  for the system.

• Allow mixed-language simulation—Allows a mixed language simulation model generation. If turned on, if a preferred simulation language is set, Qsys uses a fileset of the component for the simulation model generation. When turned off, which is the default, Qsys uses the selected language for the simulation model.

• Create testbench Qsys system—Creates a new testbench system that includes Avalon Verification Suite bus functional models (BMFs) for the exported interfaces. After generating this testbench system, you can open it in Qsys to view or modify the BFMs.

• Create testbench simulation model—Allows you to generate a simulation model in Verilog or VHDL at the same time as the testbench system. Use this option if you want to use the Qsys-generated testbench system directly.  If you want to make changes to the Qsys-generated system, open the testbench system in Qsys to make the changes and then generate a simulation model for that system.

You can turn on or off the following synthesis files for generation:

• Create HDL design files for synthesis—Creates Verilog or VHDL design files, as specified by the developers of the components and IP cores in the system. Qsys interconnect uses Verilog HDL code.

• Top-level module language for synthesis—Creates the top-level module in the system in the selected language.

• Create Block Symbol File (.bsf)—You can optionally create a (.bsf) file  to use in schematic Block Diagram File (.bdf) designs.

By default, Qsys places the output files in a subdirectory of your project directory. To change the output directory, use the Path box, or browse to locate an alternate directory. Each generation target is generated into a unique subdirectory, as shown on the Generation tab.