The Create simulation model option creates your simulation model file and scripts in the specified output directory for simulation. The simulation model includes various files and matches the system design hierarchy, with one top-level file, and potentially many child modules and files.

To generate a simulation model, follow these steps:

1. In Qsys, in the Generation dialog box, in the Create simulation model list, select Verilog or VHDL.

2. Click Generate.

Important: Qsys can generate a simulation model for the top-level design and Qsys interconnect in either Verilog HDL or VHDL. When Qsys creates a simulation model, each IP component must provide a simulation model for the selected simulation language. If any of the IP cores in the system do not provide a simulation model for the selected language, the simulation model is incomplete.

To generate a Qsys system for synthesis, in the Generation dialog box:

1. Select Create HDL design files for synthesis option to create Verilog or VHDL design files, as specified by the developers of the components and IP cores in the system.

2. Select VERILOG or VHDL for the Top-level module language for synthesis option.

3. Select Create Block Symbol File (.bsf) option to optionally create a .bsf file to use in a schematic block. You can turn off this option if you do not use schematic design files.

4. Click Generate.

The Qsys generated testbench system adds an instance of your Qsys system as a child instance, and then connects the exported top-level interfaces from your system to Bus Function Models (BFMs) that are configured to match the exported interfaces. With this testbench system, you can write a test program that provides transaction stimulus to the BFMs. Your test program accounts for the specific interface configuration.

Follow these steps to generate a standard testbench system:

1. In the Generation dialog box, set Create testbench Qsys system to either Standard,  BFMs for standard Qsys Interconnect to create a testbench with BFM components attached to exported Avalon and AXI3 interfaces, or Simple, BFMs for clocks and resets to create a testbench with only clocks and reset BFMs.

2. After Qsys creates the testbench system, you can create a simulation model for the testbench system, and specify a Verilog or VHDL top-level simulation model file. If you do not want to modify the testbench system before generating a system model, set the Create testbench simulation model option to Verilog or VHDL. If you set this option to None, the simulation model is not created.

3. Click Generate.

Important: If a Qsys system contains Avalon BFMs, VHDL simulation models are not supported because the BFM components are not available in VHDL. Only the simple testbench with clock and reset is supported for VHDL simulation.

4. Optionally, to view or modify the testbench system, open the <qsys_system>_tb.qsys file in the <qsys_ system>/testbench subdirectory. You can then make changes such as the following:

1. • Rename the BFMs to match your simulation environment.

   • Change the BFM settings to ensure adequate test coverage.

   • Replace the default BFMs with custom test components or models.

Note: If you make changes to the testbench system, you must create new simulation model files for the modified system. In the Generation dialog box, set Create simulation model to Verilog or VHDL to generate the simulation model for the system that you have modified.

1. Type the following command available in the <Quartus II installation directory>\quartus\sopc_builder\bin directory, for help on generating a system using the command line:

ip-generate --help

2. Use the command ip-make-simscript available in the <Quartus II installation directory>\quartus\sopc_builder\bin\ to create a simulator setup script based on your generated simulation model. For example, you can use the --compile-to-work option of the ip-make-simscript command if you want to use a single directory for your simulation files rather than the default generation structure.

3. Type the following command for help on regenerating simulation files using the command line:

ip-make-simscript --help