Qsys is a system integration tool included as part of the Quartus® II software. Qsys captures system-level hardware designs at a high level of abstraction and automates the task of defining and integrating customized HDL components, which may include IP cores, verification IP, and other design modules. Qsys facilitates design reuse by packaging and making available your custom components and systems, and integrates your custom components with Altera® and third-party developer components.

Qsys automatically creates interconnect logic from the connectivity options you specify, eliminating the error-prone and time-consuming task of writing HDL to specify the system-level connections.

Qsys uses standard Avalon®, AMBA® AXI3™ (version 1.0) and AMBA AXI4™ (version 2.0) interfaces that you can use to create your custom IP components. Connections between Avalon and AXI interfaces are allowed and can be achieved without requiring the use of bridges; Qsys interconnect provides the necessary bridging logic.

Qsys interconnect supports full 64-bit addressing for all Qsys interfaces and components, with a range of 0x0000 0000 0000 0000 to 0xFFFF FFFF FFFF FFFF, inclusive. This includes support for Avalon masters and slaves, AXI3 masters and slaves, and AXI4 masters and slaves, memory-mapped, bridges, translators, adapters, agents, and routers.

Qsys facilitates design reuse by packaging and making available your custom components and systems. You can use Qsys to integrate your own components with the components that Altera and third-party developers provide.

In Qsys, you can add instances of components, configure them, and make connections between their interfaces. After the system is created, Qsys generates HDL for the system module that instantiates the system, including the system interconnect.

You can use Qsys to construct embedded microprocessor systems that include processors, memory interfaces, and peripherals. You can also generate dataflow systems that do not include a processor. Qsys allows you to create bus topologies with multiple masters and slaves.

Double-clicking an instance in the connection panel opens the parameter editor, which allows you to configure the hardware settings. For example, for memory controllers, you can define data widths, burst sizes, trace delays, and device timings.

For some components, you can create, modify, and save custom component parameter settings as a preset file that you can then use in other Qsys systems. If a component or IP core supports presets, the Preset Editor appears on the right side of the parameter editor.