Fitter assignments allow you to achieve an optimal fit for the design and achieve timing closure. A common use of fitting assignments is to control the use of different resources on the device. For example, you may want to control the location for RAM blocks in order for the design to fit in the device. You can adjust the effort of the Fitter to increase or decrease the speed of the fitting process, but there can be a reduction in fMAX with increased Fitter speed. In order to increase design performance, you can adjust advanced options, such as physical synthesis settings.

In the Quartus II software you can create project-wide Fitter assignments in the Fitter Settings page of the Settings dialog box, or you can use the Assignment Editor to create assignments to individual nodes and entities.

Supported devices(Stratix III, Stratix IV, and Stratix V)  have a hierarchical clock network optimized for a large number of low-skew global clocks typical in high-speed systems. The clock network, together with optimized memory blocks, allow you to separate the design into local clock regions. The same devices are also optimized for a large number of low-skew regional clocks for enhanced peripheral and non-peripheral logic performance. Regional clocking allows you to use different clocks for I/O pins and non-peripheral logic to efficiently run peripheral and non-peripheral logic at different clock frequencies without sacrificing device-wide global clock resources.

Depending on your device family selection, you can choose from several types of clock networks including, regional, fast regional, dual-regional, dual-fast regional, global, and interquad clocks.

For devices that support periphery clocks, additional clock spine muxing restrictions limit the total number of possible clocks. Global clocks feed the entire device, whereas regional, fast regional, dual-regional, dual-fast regional, and periphery clocks feed only a predefined section of the device. Any fast regional and dual-fast regional clock assignments assigned to devices that do not contain those types of clock networks are converted to regional and dual-regional, respectively. You can access these clock networks with the Global Signal logic option.