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PL32G_EXT_CAP_HDR_REG
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0x0 |
DisplayName: Physical Layer 32.0 GT/s Extended Capability Header.
Register Size: 32
Value After Reset: 0x25c1002a
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This register provides information about Capability ID, Version, and next offset. |
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PL32G_CAPABILITY_REG
|
0x4 |
DisplayName: 32.0 GT/s Capabilities Register.
Register Size: 32
Value After Reset: 0x1
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This register provides Extended Capability of 32.0 GT/s Equalization. |
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PL32G_CONTROL_REG
|
0x8 |
DisplayName: 32.0 GT/s Control Register.
Register Size: 32
Value After Reset: 0x0
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This register controls the 32.0 GT/s capabilities. |
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PL32G_STATUS_REG
|
0xc |
DisplayName: 32.0 GT/s Status Register.
Register Size: 32
Value After Reset: 0x200
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This register provides information related to 32.0 GT/s equalization. |
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PL32G_RCVD_MOD_TS_DATA1_REG
|
0x10 |
DisplayName: Received Modified TS Data 1 Register.
Register Size: 32
Value After Reset: 0x0
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This register contains the values received in the Modified TS1/TS2 Ordered Set.
If PCI Express (Usage Mode 0) is the only one supported by a Port, this register is permitted to be hardwired to 0000 0000h by the controller. |
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PL32G_RCVD_MOD_TS_DATA2_REG
|
0x14 |
DisplayName: Received Modified TS Data 2 Register.
Register Size: 32
Value After Reset: 0x0
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This register contains the values received in Symbols 12 through 14 of the Modified TS1/TS2.
If Modified TS Usage Mode 1 Supported - Training Set Message and Modified TS Usage Mode 2 Supported - Alternate Protocol are both Clear, this register is permitted to be hardwired to 0000 0000h by the controller. |
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PL32G_TX_MOD_TS_DATA1_REG
|
0x18 |
DisplayName: Transmitted Modified TS Data 1 Register.
Register Size: 32
Value After Reset: 0x0
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This register contains the values transmitted in the Modified TS1/TS2 Ordered Set.
If PCI Express (Usage Mode 0) is the only one supported by a Port, this register is permitted to be hardwired to 0000 0000h by the controller. |
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PL32G_TX_MOD_TS_DATA2_REG
|
0x1c |
DisplayName: Transmitted Modified TS Data 2 Register.
Register Size: 32
Value After Reset: 0x0
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This register contains the values transmitted in Symbols 12 through 14 of the Modified TS1/TS2.
If Modified TS Usage Mode 1 Supported - Training Set Message and Modified TS Usage Mode 2 Supported - Alternate Protocol are both Clear, this register is permitted to be hardwired to 0000 0000h by the controller. |
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PL32G_CAP_OFF_20H_REG
|
0x20 |
DisplayName: 32.0 GT/s Lane Equalization Control Register for Lane 0-3.
Register Size: 32
Value After Reset: 0x40404040
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This register consists of control fields required for Lane 0-3 32.0 GT/s equalization. |
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PL32G_CAP_OFF_24H_REG
|
0x24 |
DisplayName: 32.0 GT/s Lane Equalization Control Register for Lane 4-7.
Register Size: 32
Value After Reset: 0x40404040
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This register consists of control fields required for Lane 4-7 32.0 GT/s equalization. |
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PL32G_CAP_OFF_28H_REG
|
0x28 |
DisplayName: 32.0 GT/s Lane Equalization Control Register for Lane 8-11.
Register Size: 32
Value After Reset: 0x40404040
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This register consists of control fields required for Lane 8-11 32.0 GT/s equalization. |
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PL32G_CAP_OFF_2CH_REG
|
0x2c |
DisplayName: 32.0 GT/s Lane Equalization Control Register for Lane 12-15.
Register Size: 32
Value After Reset: 0x40404040
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This register consists of control fields required for Lane 12-15 32.0 GT/s equalization. |