sdm_NAND_dma Address Map

Module Instance Base Address End Address
sdm_i_nand_dma 0xFFA10700 0xFFA107D3
Register Offset Width Access Reset Value Description
dma_enable 0x0 32 RW 0x00000000


                  
dma_intr 0x20 32 RW 0x00000000
DMA interrupt register 
dma_intr_en 0x30 32 RW 0x00000000
Enables corresponding interrupt bit in dma interrupt register 
target_err_addr_lo 0x40 32 RO 0x00000000
Transaction address for which controller initiator interface received an ERROR target response. 
target_err_addr_hi 0x50 32 RO 0x00000000
Transaction address for which controller initiator interface received an ERROR target response. 
flash_burst_length 0x70 32 RW 0x00000001


                  
chip_interleave_enable_and_allow_int_reads 0x80 32 RW 0x00000110


                  
no_of_blocks_per_lun 0xA0 32 RW 0x0000000F


                  
lun_status_cmd 0xB0 32 RW 0x00007878
Indicates the command to be sent while checking status of the next LUN.
chnl_active 0x60 32 RO 0x00000000
Indicates CMD-DMA channel activity status 
cmd_dma_channel_error 0xC0 32 RW 0x00000000
Bits indicating CMD-DMA channel receiving an error condition. To get more information on the error, s/w needs to read the status field of the descriptor.
cmd_dma_channel_error_en 0xD0 32 RW 0x00000000
Enable bits indicating CMD-DMA channel receiving an error condition. To get more information on the error, s/w needs to read the status field of the descriptor.
rescan_buffer_flag 0x90 32 RW 0x00000000
Rescan buffer flag.