dma_intr_en

         Enables corresponding interrupt bit in dma interrupt register 
      
Module Instance Base Address Register Address
sdm_i_nand_dma 0xFFA10700 0xFFA10730

Size: 32

Offset: 0x30

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cmddma_idle

RW 0x0

Reserved

desc_comp_channel3

RW 0x0

desc_comp_channel2

RW 0x0

desc_comp_channel1

RW 0x0

desc_comp_channel0

RW 0x0

target_error

RW 0x0

dma_intr_en Fields

Bit Name Description Access Reset
6 cmddma_idle
Interrupt processor when command DMA becomes IDLE after completing all 
                 descriptors. 
RW 0x0
4 desc_comp_channel3
 Enable bit to indicates CMD-DMA channel 3 descriptor execution done (updated when interrupt bit in cmd flags set). 
RW 0x0
3 desc_comp_channel2
 Enable bit to indicates CMD-DMA channel 2 descriptor execution done (updated when interrupt bit in cmd flags set). 
RW 0x0
2 desc_comp_channel1
 Enable bit to indicates CMD-DMA channel 1 descriptor execution done (updated when interrupt bit in cmd flags set). 
RW 0x0
1 desc_comp_channel0
 Enable bit to indicates CMD-DMA channel 0 descriptor execution done (updated when interrupt bit in cmd flags set). 
RW 0x0
0 target_error
Controller initiator interface received an ERROR target response for a transaction. 
RW 0x0