ECC Management Register Group Register Descriptions ECC error status and control for all ECC-protected HPS RAM blocks. Offset: 0x140 l2 This register is used to enable ECC on the L2 Data RAM. ECC errors can be injected into the write path using bits in this register. This register is reset by a cold reset (ignores warm reset). The interrupt status of the L2 ECC single/double bit error is handled in the General Interrupt Controller (GIC). ocram This register is used to enable ECC on the On-chip RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). usb0 This register is used to enable ECC on the USB0 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). usb1 This register is used to enable ECC on the USB1 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). emac0 This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). emac1 This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). dma This register is used to enable ECC on the DMA RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). can0 This register is used to enable ECC on the CAN0 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). can1 This register is used to enable ECC on the CAN1 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). nand This register is used to enable ECC on the NAND RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). qspi This register is used to enable ECC on the QSPI RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset). sdmmc This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected into the write path using bits in this register. Only reset by a cold reset (ignores warm reset).