ocram

This register is used to enable ECC on the On-chip RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset).
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08144

Offset: 0x144

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

derr

RW 0x0

serr

RW 0x0

injd

RW 0x0

injs

RW 0x0

en

RW 0x0

ocram Fields

Bit Name Description Access Reset
4 derr

This bit is an interrupt status bit for On-chip RAM ECC double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in On-chip RAM. Software needs to write 1 into this bit to clear the interrupt status.

RW 0x0
3 serr

This bit is an interrupt status bit for On-chip RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in On-chip RAM. Software needs to write 1 into this bit to clear the interrupt status.

RW 0x0
2 injd

Changing this bit from zero to one injects a double, non-correctable error into the On-chip RAM. This only injects one double bit error into the On-chip RAM.

RW 0x0
1 injs

Changing this bit from zero to one injects a single, correctable error into the On-chip RAM. This only injects one error into the On-chip RAM.

RW 0x0
0 en

Enable ECC for On-chip RAM

RW 0x0