Timer Module Summary

Registers in the timer module. The timer IP core supports multiple timers but it is configured for just one timer. The term Timer1 refers to this one timer in the IP core and not the module instance.

Module Instance	Base Address
`sptimer0`	`0xFFC08000`
`sptimer1`	`0xFFC09000`
`osc1timer0`	`0xFFD00000`
`osc1timer1`	`0xFFD01000`

Register Address Offset	Bit Fields
`timer1loadcount` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`timer1loadcount` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`timer1loadcount` `RW 0x0`
`timer1currentval` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`timer1currentval` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`timer1currentval` `RO 0x0`
`timer1controlreg` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`timer1_interrupt_mask` `RW 0x0`	`timer1_mode` `RW 0x0`	`timer1_enable` `RW 0x0`
`timer1eoi` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`timer1eoi` `RO 0x0`
`timer1intstat` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`timer1intstat` `RO 0x0`
`timersintstat` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`timersintstat` `RO 0x0`
`timerseoi` `0xA4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`timerseoi` `RO 0x0`
`timersrawintstat` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`timersrawintstat` `RO 0x0`
`timerscompversion` `0xAC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`timerscompversion` `RO 0x3230352A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`timerscompversion` `RO 0x3230352A`