timer1intstat

Provides the interrupt status of Timer1 after masking.
Module Instance Base Address Register Address
sptimer0 0xFFC08000 0xFFC08010
sptimer1 0xFFC09000 0xFFC09010
osc1timer0 0xFFD00000 0xFFD00010
osc1timer1 0xFFD01000 0xFFD01010

Offset: 0x10

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

timer1intstat

RO 0x0

timer1intstat Fields

Bit Name Description Access Reset
0 timer1intstat

Provides the interrupt status for Timer1. The status reported is after the interrupt mask has been applied. Reading from this register does not clear any active interrupts.

Value Description
0x0 Timer1 interrupt is not active
0x1 Timer1 interrupt is active
RO 0x0