clkmgr_perpllgrp Address Map

Module Instance	Base Address	End Address
`i_clk_mgr_perpllgrp`	`0xFFD040C0`	`0xFFD0413F`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`vco0`	`0x0`	`32`	`RW`	`0x10043`	Peripheral PLL VCO Control Register 0
`vco1`	`0x4`	`32`	`RW`	`0x10001`	Main PLL VCO Control Register
`en`	`0x8`	`32`	`RW`	`0xF7F`	Enable Register
`ens`	`0xC`	`32`	`RW`	`0xF7F`	Enable Set Register
`enr`	`0x10`	`32`	`RW`	`0xF7F`	Enable Reset Register
`bypass`	`0x14`	`32`	`RW`	`0xFF`	Bypass Register
`bypasss`	`0x18`	`32`	`RW`	`0xFF`	Bypass Set Register
`bypassr`	`0x1C`	`32`	`RW`	`0xFF`	Bypass Reset Register
`cntr2clk`	`0x28`	`32`	`RW`	`0x0`	Peripheral PLL Control Register for Counter 2 Clock
`cntr3clk`	`0x2C`	`32`	`RW`	`0x0`	Peripheral PLL Control Register for Counter 3 Clock
`cntr4clk`	`0x30`	`32`	`RW`	`0x0`	Peripheral PLL Control Register for Counter 4 Clock
`cntr5clk`	`0x34`	`32`	`RW`	`0x0`	Peripheral PLL Control Register for Counter 5 Clock
`cntr6clk`	`0x38`	`32`	`RW`	`0x0`	Peripheral PLL Control Register for Counter 6 Clock
`cntr7clk`	`0x3C`	`32`	`RW`	`0x0`	Peripheral PLL Control Register for Counter 7 Clock
`cntr8clk`	`0x40`	`32`	`RW`	`0x0`	Peripheral PLL Control Register for Counter 8 Clock
`outrst`	`0x60`	`32`	`RW`	`0x0`	Peripheral PLL Output Counter Reset Register
`outrststat`	`0x64`	`32`	`RO`	`0x0`	Peripheral PLL Output Counter Reset Ack Status Register
`emacctl`	`0x68`	`32`	`RW`	`0x0`	Main Divide Register
`gpiodiv`	`0x6C`	`32`	`RW`	`0x1`	GPIO Divide Register