cntr5clk

         Contains settings that control Counter 5 clock generated from the Peripheral PLL VCO clock.
Module Instance Base Address Register Address
i_clk_mgr_perpllgrp 0xFFD040C0 0xFFD040F4

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x0

cntr5clk Fields

Bit Name Description Access Reset
18:16 src 
Selects the source for the active 5:1 clock selection when the PLL is not bypassed.
Value Description
0 pll0_gpio_clk
1 pll1_gpio_clk
2 osc1_clk (external oscillator input pin, HPS_CLK1)
3 cb_intosc_hs_div2_clk (internal high speed oscillator divided by 2)
4 f2h_free_clk (FPGA fabric PLL clock reference)
RW 0x0
10:0 cnt 
Divides the VCO frequency by the value+1 in this field.
 RW 0x0