gpio Address Map

Module Instance	Base Address	End Address
`i_gpio_0_gpio`	`0xFFC02900`	`0xFFC029FF`
`i_gpio_1_gpio`	`0xFFC02A00`	`0xFFC02AFF`
`i_gpio_2_gpio`	`0xFFC02B00`	`0xFFCF9FFF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`gpio_swporta_dr`	`0x0`	`32`	`RW`	`0x0`	Name: Port A data register set_attribute $reg -attr RALAttribute -sub NO_BIT_BASH_TEST -value 1 Size: 1-32 bits Address Offset: 0x00 Read/Write Access: Read/Write
`gpio_swporta_ddr`	`0x4`	`32`	`RW`	`0x0`	Name: Port A Data Direction Register Size: 1-32 bits Address Offset: 0x04 Read/Write Access: Read/Write
`gpio_inten`	`0x30`	`32`	`RW`	`0x0`	Name: Interrupt enable register Size: 1-32 bits Address Offset: 0x30 Read/Write Access: Read/Write
`gpio_intmask`	`0x34`	`32`	`RW`	`0x0`	Name: Interrupt mask register Size: 1-32 bits Address Offset: 0x34 Read/Write Access: Read/Write
`gpio_inttype_level`	`0x38`	`32`	`RW`	`0x0`	Name: Interrupt level Size: 1-32 bits Address Offset: 0x38 Read/Write Access: Read/Write
`gpio_int_polarity`	`0x3C`	`32`	`RW`	`0x0`	Name: Interrupt polarity Size: 1-32 bits Address Offset: 0x3c Read/Write Access: Read/Write
`gpio_intstatus`	`0x40`	`32`	`RO`	`0x0`	Name: Interrupt status Size: 1-32 bits Address Offset: 0x40 Read/Write Access: Read/Write
`gpio_raw_intstatus`	`0x44`	`32`	`RO`	`0x0`	Name: Raw interrupt status Size: 1-32 bits Address Offset: 0x44 Read/Write Access: Read/Write
`gpio_debounce`	`0x48`	`32`	`RW`	`0x0`	Name: Debounce enable Size: 1-32 bits Address Offset: 0x48 Read/Write Access: Read/Write
`gpio_porta_eoi`	`0x4C`	`32`	`WO`	`0x0`	Name: Port A clear interrupt register Size: 1-32 bits Address Offset: 0x4c Read/Write Access: Write
`gpio_ext_porta`	`0x50`	`32`	`RO`	`0x0`	Name: Port A external port register Size: 1-32 bits Address Offset: 0x50 Read/Write Access: Read
`gpio_ls_sync`	`0x60`	`32`	`RW`	`0x0`	Name: Synchronization level Size: 1 bit Address Offset: 0x60 Read/Write Access: Read/Write
`gpio_id_code`	`0x64`	`32`	`RO`	`0x0`	Name: GPIO ID code Size: 1-32 bits Address Offset: 0x64 Read/Write Access: Read
`gpio_ver_id_code`	`0x6C`	`32`	`RO`	`0x3230392A`	Name: GPIO Component Version Size: 32 bits Address Offset: 0x6c Read/Write Access: Read
`gpio_config_reg2`	`0x70`	`32`	`RO`	`0x39CF7`	Name: GPIO Configuration Register 2 Size: 32 bits Address Offset: 0x70 Read/Write Access: Read
`gpio_config_reg1`	`0x74`	`32`	`RO`	`0x1FF0F2`	Name: GPIO Configuration Register 1 Size: 32 bits Address Offset: 0x74 Read/Write Access: Read