gpio_config_reg2

         Name: GPIO Configuration Register 2
Size: 32 bits
Address Offset: 0x70
Read/Write Access: Read
      
Module Instance Base Address Register Address
i_gpio_0_gpio 0xFFC02900 0xFFC02970
i_gpio_1_gpio 0xFFC02A00 0xFFC02A70
i_gpio_2_gpio 0xFFC02B00 0xFFC02B70

Offset: 0x70

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

encoded_id_pwidth_d

RO 0x7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

encoded_id_pwidth_d

RO 0x7

encoded_id_pwidth_c

RO 0x7

encoded_id_pwidth_b

RO 0x7

encoded_id_pwidth_a

RO 0x17

gpio_config_reg2 Fields

Bit Name Description Access Reset
19:15 encoded_id_pwidth_d
The value of this register is derived from the
GPIO_PWIDTH_D configuration parameter.
0x0 = 8 bits
0x1 = 16 bits
0x2 = 32 bits
0x3 = Reserved
Value Description
0x1c WIDTHLESSONE24BITS
0x7 WIDTHLESSONE8BITS
RO 0x7
14:10 encoded_id_pwidth_c
The value of this register is derived from the
GPIO_PWIDTH_C configuration parameter.
0x0 = 8 bits
0x1 = 16 bits
0x2 = 32 bits
0x3 = Reserved
Value Description
0x1c WIDTHLESSONE24BITS
0x7 WIDTHLESSONE8BITS
RO 0x7
9:5 encoded_id_pwidth_b
The value of this register is derived from the
GPIO_PWIDTH_B configuration parameter.
0x0 = 8 bits
0x1 = 16 bits
0x2 = 32 bits
0x3 = Reserved
Value Description
0x1c WIDTHLESSONE24BITS
0x7 WIDTHLESSONE8BITS
RO 0x7
4:0 encoded_id_pwidth_a
The value of this register is derived from the
GPIO_PWIDTH_A configuration parameter.
0x0 = 8 bits
0x1 = 16 bits
0x2 = 32 bits
0x3 = Reserved
Value Description
0x1c WIDTHLESSONE24BITS
0x7 WIDTHLESSONE8BITS
RO 0x17