ctlgrp Address Map

Contains registers with settings for internal use.


Module Instance	Base Address	End Address
`i_clk_mgr__clkmgr_csr__10d10000__ctlgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`	`0x10D100D0`	`0x10D10113`


Register	Offset	Width	Access	Reset Value	Description
`jtag`	`0x0`	`32`	`RW`	`0x00000180`	Jtag control registers for the PLLs - Testing Access
`emacactr`	`0x4`	`32`	`RW`	`0x00010001`	Main PLL Control Register for emaca_free_clk
`emacbctr`	`0x8`	`32`	`RW`	`0x00010009`	MAin PLL Control Register for emacb_free_clk
`emacptpctr`	`0xC`	`32`	`RW`	`0x00000000`	Main PLL Control Register for emac_ptp_free_clk
`gpiodbctr`	`0x10`	`32`	`RW`	`0x00000001`	Peripheral PLL Control Register for gpio_db_free_clk
`s2fuser0ctr`	`0x18`	`32`	`RW`	`0x00010000`	Control Register for s2f_user0_free_clk registers
`s2fuser1ctr`	`0x1C`	`32`	`RW`	`0x00010000`	Main PLL Control Register for s2f_user1_free_clk
`psirefctr`	`0x20`	`32`	`RW`	`0x00010000`	Main PLL Control Register for psi_ref_free_clk
`extcntrst`	`0x24`	`32`	`RW`	`0x00003CE4`	Pingpong or External Counter reset control
`usb31ctr`	`0x28`	`32`	`RW`	`0x00000013`	Control Register for usb31 clk
`dsuctr`	`0x2C`	`32`	`RW`	`0x00000000`	Control Register for dsu_clk
`core01ctr`	`0x30`	`32`	`RW`	`0x00010000`	Control Register for core01_clk
`core23ctr`	`0x34`	`32`	`RW`	`0x00000000`	Main PLL Control Register for core23_clk
`core2ctr`	`0x38`	`32`	`RW`	`0x00000000`	Control Register for core2_clk
`core3ctr`	`0x3C`	`32`	`RW`	`0x00000000`	Main PLL Control Register for core3_clk
`serial_con_pll_ctr`	`0x40`	`32`	`RW`	`0x00000000`	serial_con_pll_ctr