s2fuser0ctr

         Contains settings that control s2f_user0_free_clk generated from Main PLL.


Module Instance	Base Address	Register Address
`i_clk_mgr__clkmgr_csr__10d10000__ctlgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`	`0x10D100D0`	`0x10D100E8`

Size: 32

Offset: 0x18

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_2` `RO 0x0`													`src` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`

s2fuser0ctr Fields

Bit Name Description Access Reset

31:19

Reserved_2

Reserved bitfield added by Magillem

RO

0x0

18:16

src

Selects the source for the active 5:1 clock for s2f clock slice when the PLL is not bypassed.

Value	Description
0	MAIN
1	PERI
2	OSC1
3	INTOSC
4	FPGA

RW

0x1

15:11

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

10:0

cnt

Division setting for ping pong counter in clock slice. Divides the s2f_user0_free_clk frequency by this value + 1.

RW

0x0