ctlgrp Summary

Contains registers with settings for internal use.

Base Address: 0x10D100D0


Register Address Offset	Bit Fields
`i_clk_mgr__clkmgr_csr__10d10000__ctlgrp__SEG_L4_SHR_ClockManager_0x0_0x1000`
`jtag` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`rst` `RW 0x1`	`id` `RW 0x80`
`emacactr` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x1`
`emacbctr` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x20`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x20`					`cnt` `RW 0x9`
`emacptpctr` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`
`gpiodbctr` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x1`
`s2fuser0ctr` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`
`s2fuser1ctr` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`
`psirefctr` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`
`extcntrst` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_12` `RO 0x0`		`core3cntrst` `RW 0x1`	`core2cntrst` `RW 0x1`	`core01cntrst` `RW 0x1`	`dsucntrst` `RW 0x1`	`Reserved_8` `RO 0x0`	`usb31refcntrst` `RW 0x0`	`psirefcntrst` `RW 0x1`	`s2fuser1cntrst` `RW 0x1`	`s2fuser0cntrst` `RW 0x1`	`Reserved_4` `RO 0x0`	`gpiodbcntrst` `RW 0x0`	`emacptpcntrst` `RW 0x1`	`emacbcntrst` `RW 0x0`	`emacacntrst` `RW 0x0`
`usb31ctr` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x13`
`dsuctr` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`
`core01ctr` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`													`src` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`
`core23ctr` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`													`src` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_0` `RO 0x0`
`core2ctr` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`
`core3ctr` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`					`cnt` `RW 0x0`
`serial_con_pll_ctr` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`en` `RW 0x0`