Rlpi1 Address Map

Contains registers with the GICR1 prefix.


Module Instance	Base Address	End Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRlpi1`	`0x1D080000`	`0x1D08FFFF`


Register	Offset	Width	Access	Reset Value	Description
`GICR1_CTLR`	`0x0`	`32`	`RW`	`0x00000000`	GICR1_CTLR
`GICR1_IIDR`	`0x4`	`32`	`RO`	`0x0201743B`	GICR1_IIDR
`GICR1_TYPER`	`0x8`	`64`	`RO`	`0x0000000000000000`	GICR1_TYPER
`GICR1_WAKER`	`0x14`	`32`	`RW`	`0x00000006`	GICR1_WAKER
`GICR1_FCTLR`	`0x20`	`32`	`RW`	`0x00000000`	GICR1_FCTLR
`GICR1_PWRR`	`0x24`	`32`	`RW`	`0x0000010D`	GICR1_PWRR
`GICR1_CLASS`	`0x28`	`32`	`RW`	`0x00000000`	GICR1_CLASS
`GICR1_PROPBASER`	`0x70`	`64`	`RW`	`0x0000000000000000`	GICR1_PROPBASER
`GICR1_PENDBASER`	`0x78`	`64`	`RW`	`0x0000000000000000`	GICR1_PENDBASER
`GICR1_PIDR4`	`0xFFD0`	`32`	`RO`	`0x00000044`	GICR1_PIDR4
`GICR1_PIDR5`	`0xFFD4`	`32`	`RO`	`0x00000000`	GICR1_PIDR5
`GICR1_PIDR6`	`0xFFD8`	`32`	`RO`	`0x00000000`	GICR1_PIDR6
`GICR1_PIDR7`	`0xFFDC`	`32`	`RO`	`0x00000000`	GICR1_PIDR7
`GICR1_PIDR0`	`0xFFE0`	`32`	`RO`	`0x00000093`	GICR1_PIDR0
`GICR1_PIDR1`	`0xFFE4`	`32`	`RO`	`0x000000B4`	GICR1_PIDR1
`GICR1_PIDR2`	`0xFFE8`	`32`	`RO`	`0x0000003B`	GICR1_PIDR2
`GICR1_PIDR3`	`0xFFEC`	`32`	`RO`	`0x00000000`	GICR1_PIDR3
`GICR1_CIDR0`	`0xFFF0`	`32`	`RO`	`0x0000000D`	GICR1_CIDR0
`GICR1_CIDR1`	`0xFFF4`	`32`	`RO`	`0x000000F0`	GICR1_CIDR1
`GICR1_CIDR2`	`0xFFF8`	`32`	`RO`	`0x00000005`	GICR1_CIDR2
`GICR1_CIDR3`	`0xFFFC`	`32`	`RO`	`0x000000B1`	GICR1_CIDR3