Rlpi1 Summary

Contains registers with the GICR1 prefix.

Base Address: 0x1D080000


Register Address Offset	Bit Fields
`i_aps_gic__gic_axi4_slave__1d000000__GICRlpi1`
`GICR1_CTLR` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UWP` `RO 0x0`	`RESERVED2` `RW 0x0`				`DPG1S` `RW 0x0`	`DPG1NS` `RW 0x0`	`DPG0` `RW 0x0`	`RESERVED1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED1` `RW 0x0`												`RWP` `RO 0x0`	`RESERVED0` `RW 0x0`		`EnableLPIs` `RW 0x0`
`GICR1_IIDR` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ProductID` `RO 0x2`								`RESERVED0` `RO 0x0`				`Variant` `RO 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Revision` `RO 0x7`				`Implementer` `RO 0x43B`
`GICR1_TYPER` `0x8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`AffinityValue` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`AffinityValue` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED2` `RO 0x0`						`CommonLPIAff` `RO 0x0`		`ProcessorNumber` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ProcessorNumber` `RO 0x0`								`RESERVED1` `RO 0x0`		`DPGS` `RO 0x0`	`Last` `RO 0x0`	`DirectLPI` `RO 0x0`	`RESERVED0` `RO 0x0`	`VLPIS` `RO 0x0`	`PLPIS` `RO 0x0`
`GICR1_WAKER` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Quiescent` `RO 0x0`	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`													`ChildrenAsleep` `RO 0x1`	`ProcessorSleep` `RW 0x1`	`Sleep` `RW 0x0`
`GICR1_FCTLR` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`QD` `RW 0x0`	`RESERVED1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED1` `RW 0x0`									`CGO` `RW 0x0`			`RESERVED0` `RW 0x0`			`SIP` `RW 0x0`
`GICR1_PWRR` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED1` `RO 0x0`								`RDG` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RDG` `RO 0x0`	`RDGO` `RO 0x1`							`RESERVED0` `RO 0x0`				`RDGPO` `RO 0x1`	`RDGPD` `RW 0x1`	`RDAG` `WO 0x0`	`RDPD` `RW 0x1`
`GICR1_CLASS` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RW 0x0`															`Class` `RW 0x0`
`GICR1_PROPBASER` `0x112` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RESERVED2` `RW 0x0`					`OuterCacheability` `RW 0x0`			`RESERVED1` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RESERVED1` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PhysicalAddress` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PhysicalAddress` `RW 0x0`				`Shareability` `RW 0x0`		`Cacheability` `RW 0x0`			`RESERVED0` `RW 0x0`		`IDBits` `RW 0x0`
`GICR1_PENDBASER` `0x120` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RESERVED4` `RW 0x0`	`PendingTableZero` `RW 0x0`	`RESERVED3` `RW 0x0`			`OuterCacheability` `RW 0x0`			`RESERVED2` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RESERVED2` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PhysicalAddress` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED1` `RW 0x0`				`Shareability` `RW 0x0`		`Cacheability` `RW 0x0`			`RESERVED0` `RW 0x0`
`GICR1_PIDR4` `0x65488` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`SIZE` `RO 0x4`				`DES_2` `RO 0x4`
`GICR1_PIDR5` `0x65492` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`RESERVED` `RO 0x0`
`GICR1_PIDR6` `0x65496` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`RESERVED` `RO 0x0`
`GICR1_PIDR7` `0x65500` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`RESERVED` `RO 0x0`
`GICR1_PIDR0` `0x65504` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`PART_0` `RO 0x93`
`GICR1_PIDR1` `0x65508` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`DES_0` `RO 0xB`				`PART_1` `RO 0x4`
`GICR1_PIDR2` `0x65512` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`REVISION` `RO 0x3`				`JEDEC` `RO 0x1`	`DES_1` `RO 0x3`
`GICR1_PIDR3` `0x65516` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED1` `RO 0x0`								`REVAND` `RO 0x0`				`RESERVED0` `RO 0x0`	`CMOD` `RO 0x0`
`GICR1_CIDR0` `0x65520` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`PRMBL_0` `RO 0xD`
`GICR1_CIDR1` `0x65524` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`CLASS` `RO 0xF`				`PRMBL_1` `RO 0x0`
`GICR1_CIDR2` `0x65528` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`PRMBL_2` `RO 0x5`
`GICR1_CIDR3` `0x65532` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESERVED0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESERVED0` `RO 0x0`								`PRMBL_3` `RO 0xB1`