OSC1TIMER1 Summary

DW_apb_timers address block

Base Address: 0x10D00100


Register Address Offset	Bit Fields
`i_timer_sys_1__timer_csr__10d00100__DW_apb_timers_addr_block__SEG_L4_SYS1_rti1_0x0_0x100`
`TIMER1LOADCOUNT` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMER1LOADCOUNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMER1LOADCOUNT` `RW 0x0`
`TIMER1CURRENTVAL` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMER1CURRENTVAL` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMER1CURRENTVAL` `RO 0x0`
`TIMER1CONTROLREG` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`													`TIMER_INTERRUPT_MASK` `RW 0x0`	`TIMER_MODE` `RW 0x0`	`TIMER_ENABLE` `RW 0x0`
`TIMER1EOI` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`TIMER1EOI` `RO 0x0`
`TIMER1INTSTAT` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`TIMER1INTSTAT` `RO 0x0`
`TIMERSINTSTAT` `0x160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`TIMERSINTSTAT` `RO 0x0`
`TIMERSEOI` `0x164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`TIMERSEOI` `RO 0x0`
`TIMERSRAWINTSTAT` `0x168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`TIMERSRAWINTSTAT` `RO 0x0`
`TIMERSCOMPVERSION` `0x172` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMERSCOMPVERSION` `RO 0x3230392A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMERSCOMPVERSION` `RO 0x3230392A`