TIMER1INTSTAT
Name: Timer1 Interrupt Status Register
Size: 1 bit
Address Offset: 16
Read/Write Access: Read
| Module Instance | Base Address | Register Address |
|---|---|---|
i_timer_sys_1__timer_csr__10d00100__DW_apb_timers_addr_block__SEG_L4_SYS1_rti1_0x0_0x100
|
0x10D00100
|
0x10D00110
|
Size: 32
Offset: 0x10
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
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TIMER1INTSTAT Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:1 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
||||||
| 0 |
TIMER1INTSTAT
|
Contains the interrupt status for Timer1.
|
RO
|
0x0
|