L4_per_scr Address Map
L4_PER Security Control Registers (SCR)
Module Instance | Base Address | End Address |
---|---|---|
noc_fw_l4_per__ocp_slv__10d21000__l4_per_scr
|
0x10D21000
|
0x10D210FF
|
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
nand_register
|
0x0
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for nand register |
usb0_register
|
0xC
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for usb0_register |
usb1_register
|
0x10
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for usb1_register |
spi_master0
|
0x1C
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for spi_master0 |
spi_master1
|
0x20
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for spi_master1 |
spi_slave0
|
0x24
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for spi_slave0 |
spi_slave1
|
0x28
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for spi_slave1 |
emac0
|
0x2C
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for emac0 |
emac1
|
0x30
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for emac1 |
emac2
|
0x34
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for emac2 |
sdmmc
|
0x40
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for sdmmc |
gpio0
|
0x44
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for gpio0 |
gpio1
|
0x48
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for gpio1 |
i2c0
|
0x50
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for i2c0 |
i2c1
|
0x54
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for i2c1 |
i2c2
|
0x58
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for i2c2 |
i2c3
|
0x5C
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for i2c3 |
i2c4
|
0x60
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for i2c4 |
sp_timer0
|
0x64
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for sp_timer0 |
sp_timer1
|
0x68
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for sp_timer1 |
uart0
|
0x6C
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for uart0 |
uart1
|
0x70
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for uart1 |
i3c0
|
0x74
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for i3c0 |
i3c1
|
0x78
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for i3c1 |
dma0
|
0x7C
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for dma0 |
dma1
|
0x80
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for dma1 |
combo_phy
|
0x84
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for combo_phy |
nand_sdma
|
0x88
|
32
|
RW
|
0x00000000
|
Per-Master Security bit for nand_sdma |