gpio1 

         Per-Master Security bit for gpio1
Module Instance Base Address Register Address
noc_fw_l4_per__ocp_slv__10d21000__l4_per_scr 0x10D21000 0x10D21048

Size: 32

Offset: 0x48

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_5

RO 0x0

axi_ap

RW 0x0

Reserved_4

RO 0x0

fpga2soc

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_3

RO 0x0

dmam1

RW 0x0

dma

RW 0x0

Reserved_1

RO 0x0

mpu

RW 0x0

gpio1 Fields

Bit Name Description Access Reset
31:25 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
24 axi_ap 
Security bit configuration for transactions from axi_ap to gpio1. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
23:17 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
16 fpga2soc 
Security bit configuration for transactions from fpga2soc to gpio1. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
15:10 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
9 dmam1 
Security bit configuration for transactions from dmam1 to gpio1. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
8 dma 
Security bit configuration for transactions from dma to gpio1. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
7:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 mpu 
Security bit configuration for transactions from mpu to gpio1. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0