L4_per_scr Summary

L4_PER Security Control Registers (SCR)

Base Address: 0x10D21000


Register Address Offset	Bit Fields
`noc_fw_l4_per__ocp_slv__10d21000__l4_per_scr`
`nand_register` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`usb0_register` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`usb1_register` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`spi_master0` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`spi_master1` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`spi_slave0` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`spi_slave1` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`emac0` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`emac1` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`emac2` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`sdmmc` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`gpio0` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`gpio1` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`i2c0` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`i2c1` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`i2c2` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`i2c3` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`i2c4` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`sp_timer0` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`sp_timer1` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`uart0` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`uart1` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`i3c0` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`i3c1` `0x120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`dma0` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`dma1` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`combo_phy` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`nand_sdma` `0x136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`