DMAC1_Channel1 Address Map

DW_axi_dmac Channel 1 register address block


Module Instance	Base Address	End Address
`i_dma__dmac1_ahb_slv__10dc0000__Channel1_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000`	`0x10DC0100`	`0x10DC019F`


Register	Offset	Width	Access	Reset Value	Description
`CH1_SAR`	`0x0`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Source Address Register
`CH1_DAR`	`0x8`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Destination Address Register
`CH1_BLOCK_TS`	`0x10`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Block Transfer Size Register
`CH1_CTL`	`0x18`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Control Register
`CH1_CFG2`	`0x20`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Configuration Register 2
`CH1_LLP`	`0x28`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Linked List Pointer Register
`CH1_STATUSREG`	`0x30`	`64`	`RO`	`0x0000000000000000`	DW_axi_dmac Channel x Status Register
`CH1_SWHSSRCREG`	`0x38`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Software Handshake Source Register
`CH1_SWHSDSTREG`	`0x40`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Software Handshake Destination Register
`CH1_BLK_TFR_RESUMEREQREG`	`0x48`	`64`	`WO`	`0x0000000000000000`	DW_axi_dmac Channel x Block Transfer Resume Request Register
`CH1_AXI_IDREG`	`0x50`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x AXI ID Register
`CH1_AXI_QOSREG`	`0x58`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x AXI QoS Register
`CH1_INTSTATUS_ENABLEREG`	`0x80`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Interrupt Status Enable Register
`CH1_INTSTATUS`	`0x88`	`64`	`RO`	`0x0000000000000000`	DW_axi_dmac Channel x Interrupt Status Register
`CH1_INTSIGNAL_ENABLEREG`	`0x90`	`64`	`RW`	`0x0000000000000000`	DW_axi_dmac Channel x Interrupt Signal Enable Register
`CH1_INTCLEARREG`	`0x98`	`64`	`WO`	`0x0000000000000000`	DW_axi_dmac Channel x Interrupt Status Clear Register