CH1_CTL 

         This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled, the CHx_CTL register is loaded from the corresponding location of the LLI and it can be varied on a block-by-block basis within a DMA transfer. The software is not allowed to directly update this register through DW_axi_dmac slave interface. Any write to this register during LLI based multi-block transfer is ignored.
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Channel1_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0100 0x10DC0118

Size: 64

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

SHADOWREG_OR_LLI_VALID

RW 0x0

SHADOWREG_OR_LLI_LAST

RW 0x0

RSVD_DMAC_CHx_CTL_59to61

RO 0x0

IOC_BlkTfr

RW 0x0

DST_STAT_EN

RO 0x0

SRC_STAT_EN

RO 0x0

AWLEN

RW 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

AWLEN_EN

RW 0x0

ARLEN

RW 0x0

ARLEN_EN

RW 0x0

AW_PROT

RW 0x0

AR_PROT

RW 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_DMAC_CHx_CTL_31

RO 0x0

NonPosted_LastWrite_En

RW 0x0

AW_CACHE

RW 0x0

AR_CACHE

RW 0x0

DST_MSIZE

RW 0x0

SRC_MSIZE

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SRC_MSIZE

RW 0x0

DST_TR_WIDTH

RW 0x0

SRC_TR_WIDTH

RW 0x0

RSVD_DMAC_CHx_CTL_7

RO 0x0

DINC

RW 0x0

RSVD_DMAC_CHx_CTL_5

RO 0x0

SINC

RW 0x0

RSVD_DMAC_CHx_CTL_3

RO 0x0

DMS

RO 0x0

RSVD_DMAC_CHx_CTL_1

RO 0x0

SMS

RO 0x0

CH1_CTL Fields

Bit Name Description Access Reset
63 SHADOWREG_OR_LLI_VALID 
Shadow Register content/Linked List Item valid.
Indicates whether the content of shadow register or the linked list item fetched from the memory is valid.
 - 0: Shadow Register content/LLI is invalid.
 - 1: Last Shadow Register/LLI is valid.
LLI based multi-block transfer: The CHx_CTL register is loaded from the LLI. Hence, the software is not allowed to directly update this register through the DW_axi_dmac slave
interface.
This field can be used to dynamically extend the LLI by the software. On noticing this bit as 0, DW_axi_dmac discards the LLI and generates the ShadowReg_Or_LII_Invalid_ERR Interrupt if
the corresponding channel error interrupt mask bit is set to 0.
In the case of LLI pre-fetching, the ShadowReg_Or_LLI_Invalid_ERR interrupt is not generated even if the ShadowReg_Or_LLI_Valid bit
is seen to be 0 for the pre-fetched LLI. In this case, DW_axi_dmac attempts the LLI fetch operation again after completing the current block transfer and generates the ShadowReg_Or_LII_Invalid_ERR
interrupt only if ShadowReg_Or_LII_Valid bit is still seen to be 0.
This error condition causes the DW_axi_dmac to halt the corresponding channel gracefully. DW_axi_dmac waits until software writes
(any value) to CHx_BLK_TFR_ResumeReqReg to indicate valid LLI availability before attempting another LLI read operation. This bit is cleared to 0 and written back to the corresponding LLI location
after block transfer completion when LLI write-back option is enabled. Hence, for LLI-based multi-block transfers, the software might manipulate/redefine any descriptor with the ShadowReg_Or_LII_Valid
bit set to 0 if LLI write-back option is enabled.
Shadow Reg based multi-block transfer: On noticing this bit as 0 during shadow register fetch phase, DW_axi_dmac discards the Shadow Register
contents and generates ShadowReg_Or_LLI_Invlid_ERR Interrupt. In this case, the software has to write (any value) to CHx_BLK_TFR_ResumeReqReg after updating the shadow registers and after setting
ShadowReg_Or_LLI_Valid bit to 1 to indicate to DW_axi_dmac that shadow register contents are valid and the next block transfer can be resumed.
DW_axi_dmac clears this bit to 0 after copying the
shadow register contents. Software can reprogram the shadow registers only if ShadowReg_Or_LLI_Valid bit is 0. Software needs to read this register in block completion interrupt service routine (if
interrupt is enabled)/continuously poll this register (if interrupt is not enabled) to make sure that this bit is 0 before updating the shadow registers.
If shadow-register-based multi-block
transfer is enabled and software attempts to write to the shadow register when ShadowReg_Or_LLI_Valid bit is 1, DW_axi_dmac generates SLVIF_ShadowReg_WrOnValid_ERR interrupt.
Value Description
0x0 Indicates shadowreg/LLI content is Invalid
0x1 Indicates shadowreg/LLI content is Valid
RW 0x0
62 SHADOWREG_OR_LLI_LAST 
Last Shadow Register/Linked List Item.
Indicates whether shadow register content or the linked list item fetched from the memory is the last one or not.
 - 0: Not last Shadow Register/LLI
 - 1: Last Shadow Register/LLI

LLI based multi-block transfer: DW_axi_dmac uses this bit to decide if another LLI fetch is needed in the current DMA transfer.
 - If this bit is 0, DW_axi_dmac fetches the next LLI from the address pointed out by LLP field in the current LLI.
 - If this bit is 1, DW_axi_dmac understands that current block is the final block in the dma transfer and ends the dma transfer once the AMBA transfer corresponding to the current block completes.
Shadow Reg based multi-block transfer: DW_axi_dmac uses this bit to decide if another Shadow Register fetch is needed in the current DMA transfer.
 - If this bit is 0, DW_axi_dmac understands that there are one or more blocks to be transferred in the current block and hence one or more shadow register set contents will be valid and needs to be fetched.
 - If this bit is 1, DW_axi_dmac understands that current block is the final block in the dma transfer and ends the dma transfer once the AMBA transfer corresponding to the current block completes.
Value Description
0x0 Indicates shadowreg/LLI content is not the last one
0x1 Indicates shadowreg/LLI content is the last one
RW 0x0
61:59 RSVD_DMAC_CHx_CTL_59to61 
DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only
 RO 0x0
58 IOC_BlkTfr 
Interrupt On completion of Block Transfer
This bit is used to control the block transfer completion interrupt generation on a block by block
basis for shadow register or linked list based multi-block transfers. Writing 1 to this register field enables CHx_IntStatusReg.BLOCK_TFR_DONE_IntStat field if this interrupt generation is enabled in
CHx_IntStatus_EnableReg register and the external interrupt output is is asserted if this interrupt generation is enabled in CHx_IntSignal_EnableReg register.
Note: If a linked-list or
shadow-register-based multi-block transfer is not used for both source and destination (for instance if source and destination use contiguous address or auto-reload-based multi-block transfer), the
value of this field cannot be modified per block. Additionally, the value programmed before the channel is enabled is used for all the blocks in the DMA transfer.
Value Description
0x0 Disables CHx_IntStatusReg.BLOCK_TFR_DONE_IntStat field
0x1 Enables CHx_IntStatusReg.BLOCK_TFR_DONE_IntStat field
RW 0x0
57 DST_STAT_EN 
Destination Status Enable
Enable the logic to fetch status from destination peripheral of channel x pointed to by the content of CHx_DSTATAR register and stores it in CHx_DSTAT register. This value is written back to the CHx_DSTAT location of linked list at end of each block transfer if DMAX_CHx_LLI_WB_EN is set to 1 and if linked list based multi-block transfer is used by either source or destination peripheral.
Value Description
0x0 No status fetch for Destination device
0x1 Enables status fetch for Destination and store the value in CH1_DSTAT register
RO 0x0
56 SRC_STAT_EN 
Source Status Enable
Enable the logic to fetch status from source peripheral of channel x pointed to by the content of CHx_SSTATAR register and stores it in CHx_SSTAT register. This value is written back to the CHx_SSTAT location of linked list at end of each block transfer if DMAX_CHx_LLI_WB_EN is set to 1 and if linked list based multi-block transfer is used by either source or destination peripheral.
Value Description
0x0 No status fetch for Source device
0x1 Enables status fetch for Source and store the value in CH1_SSTAT register
RO 0x0
55:48 AWLEN 
Destination Burst Length
AXI Burst length used for destination data transfer. The specified burst length is used for destination data transfer
till the extent possible; remaining transfers use maximum possible value that is less than or equal to DMAX_CHx_MAX_AMBA_BURST_LENGTH.
The maximum value of AWLEN is limited by
DMAX_CHx_MAX_AMBA_BURST_LENGTH.
Note: The AWLEN setting may not be honored towards end-to-block transfers, the end of a transaction (only applicable to non-memory peripharals), and during
4K boundary crossings.
 RW 0x0
47 AWLEN_EN 
Destination Burst Length Enable
If this bit is set to 1, DW_axi_dmac uses the value of CHx_CTL.AWLEN as AXI Burst length for destination data
transfer till the extent possible; remaining transfers use maximum possible burst length.
If this bit is set to 0, DW_axi_dmac uses any possible value which is less than or equal to DMAX_CHx_MAX_AMBA_BURST_LENGTH as AXI Burst length for destination data transfer.
Value Description
0x0 AXI Burst Length is any possible value <= DMAX_CH1_MAX_AMBA_BURST_LENGTH for Destination data transfers
0x1 AXI Burst Length is CH1_CTL.AWLEN (till the extent possible) for Destination data transfers
RW 0x0
46:39 ARLEN 
Source Burst Length
AXI Burst length used for source data transfer. The specified burst length is used for source data transfer till the extent
possible; remaining transfers use maximum possible value that is less than or equal to DMAX_CHx_MAX_AMBA_BURST_LENGTH.
The maximum value of ARLEN is limited by DMAX_CHx_MAX_AMBA_BURST_LENGTH
 RW 0x0
38 ARLEN_EN 
Source Burst Length Enable
If this bit is set to 1, DW_axi_dmac uses the value of CHx_CTL.ARLEN as AXI Burst length for source data transfer
till the extent possible; remaining transfers use maximum possible burst length.
If this bit is set to 0, DW_axi_dmac uses any possible value that is less than or equal to DMAX_CHx_MAX_AMBA_BURST_LENGTH as AXI Burst length for source data transfer.
Value Description
0x0 AXI Burst Length is any possible value <= DMAX_CH1_MAX_AMBA_BURST_LENGTH for Source data transfers
0x1 AXI Burst Length is CH1_CTL.ARLEN (till the extent possible) for Source data transfers
RW 0x0
37:35 AW_PROT 
AXI 'aw_prot' signal
 RW 0x0
34:32 AR_PROT 
AXI 'ar_prot' signal
 RW 0x0
31 RSVD_DMAC_CHx_CTL_31 
DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only
 RO 0x0
30 NonPosted_LastWrite_En 
Non Posted Last Write Enable
This bit decides whether posted writes can be used throughout the block transfer.
 - 0: Posted writes may be used throughout the block transfer.
 - 1: Posted writes may be used till the end of the block (inside a block) and the last write in the block must be non-posted. This is to synchronize block completion interrupt generation to the last write data reaching the end memory/peripheral.
Value Description
0x0 Posted writes may be used throughout the block transfer
0x1 Last write in the block must be non-posted
RW 0x0
29:26 AW_CACHE 
AXI 'aw_cache' signal
 RW 0x0
25:22 AR_CACHE 
AXI 'ar_cache' signal
 RW 0x0
21:18 DST_MSIZE 
Destination Burst Transaction Length.
Number of data items, each of width CHx_CTL.DST_TR_WIDTH, to be written to the destination every time a
destination burst transaction request is made from the corresponding hardware or software handshaking interface.Note: This Value is not related to the AXI awlen signal.
Value Description
0x0 1 Data Item read from Destination in the burst transaction
0x1 4 Data Item read from Destination in the burst transaction
0x2 8 Data Item read from Destination in the burst transaction
0x3 16 Data Item read from Destination in the burst transaction
0x4 32 Data Item read from Destination in the burst transaction
0x5 64 Data Item read from Destination in the burst transaction
0x6 128 Data Item read from Destination in the burst transaction
0x7 256 Data Item read from Destination in the burst transaction
0x8 512 Data Item read from Destination in the burst transaction
0x9 1024 Data Item read from Destination in the burst transaction
RW 0x0
17:14 SRC_MSIZE 
Source Burst Transaction Length.
Number of data items, each of width CHx_CTL.SRC_TR_WIDTH, to be read from the source every time a source
burst transaction request is made from the corresponding hardware or software handshaking interface. The maximum value of DST_MSIZE is limited by DMAX_CHx_MAX_MSIZE.
Note: This Value is not related to the AXI arlen signal.
Value Description
0x0 1 Data Item read from Source in the burst transaction
0x1 4 Data Item read from Source in the burst transaction
0x2 8 Data Item read from Source in the burst transaction
0x3 16 Data Item read from Source in the burst transaction
0x4 32 Data Item read from Source in the burst transaction
0x5 64 Data Item read from Source in the burst transaction
0x6 128 Data Item read from Source in the burst transaction
0x7 256 Data Item read from Source in the burst transaction
0x8 512 Data Item read from Source in the burst transaction
0x9 1024 Data Item read from Source in the burst transaction
RW 0x0
13:11 DST_TR_WIDTH 
Destination Transfer Width.
Mapped to AXI bus awsize, this value must be less than or equal to DMAX_M_DATA_WIDTH.
Value Description
0x0 Destination Transfer Width is 8 bits
0x1 Destination Transfer Width is 16 bits
0x2 Destination Transfer Width is 32 bits
0x3 Destination Transfer Width is 64 bits
0x4 Destination Transfer Width is 128 bits
0x5 Destination Transfer Width is 256 bits
0x6 Destination Transfer Width is 512 bits
RW 0x0
10:8 SRC_TR_WIDTH 
Source Transfer Width.
Mapped to AXI bus arsize, this value must be less than or equal to DMAX_M_DATA_WIDTH.
Value Description
0x0 Source Transfer Width is 8 bits
0x1 Source Transfer Width is 16 bits
0x2 Source Transfer Width is 32 bits
0x3 Source Transfer Width is 64 bits
0x4 Source Transfer Width is 128 bits
0x5 Source Transfer Width is 256 bits
0x6 Source Transfer Width is 512 bits
RW 0x0
7 RSVD_DMAC_CHx_CTL_7 
DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only
 RO 0x0
6 DINC 
Destination Address Increment.
Indicates whether to increment the destination address on every destination transfer. If the device is writing data from a source peripheral FIFO with a fixed address, then set this field to 'No change'.
 - 0: Increment 
 - 1: No Change
NOTE: Increment aligns the address to the next CHx_CTL.DST_TR_WIDTH boundary.
Value Description
0x0 Destination address incremented on every source transfer
0x1 Destination address is fixed
RW 0x0
5 RSVD_DMAC_CHx_CTL_5 
DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only
 RO 0x0
4 SINC 
Source Address Increment.
Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to 'No change'.
 - 0: Increment 
 - 1: No Change
NOTE: Increment aligns the address to the next CHx_CTL.SRC_TR_WIDTH boundary.
Value Description
0x0 Source address incremented on every source transfer
0x1 Source address is fixed
RW 0x0
3 RSVD_DMAC_CHx_CTL_3 
DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only
 RO 0x0
2 DMS 
Destination Master Select.
Identifies the Master Interface layer from which the destination device (peripheral or memory) is accessed.
 - 0: AXI master 1 
 - 1: AXI Master 2
Value Description
0x0 Destination device on Master-1 interface layer
0x1 Destination device on Master-2 interface layer
RO 0x0
1 RSVD_DMAC_CHx_CTL_1 
DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only
 RO 0x0
0 SMS 
Source Master Select.
Identifies the Master Interface layer from which the source device (peripheral or memory) is accessed.
 - 0: AXI master 1 
 - 1: AXI Master 2
Value Description
0x0 Source device on Master-1 interface layer
0x1 Source device on Master-2 interface layer
RO 0x0