1EMAC1_DWCXG_CORE Summary

MAC Protocol-Core Registers.

Base Address: 0x10820000


Register Address Offset	Bit Fields
`u_emac1__apb_reg_config_slave__10820000__DWCXG_CORE__SEG_L4_MP_emac1_s_0x0_0x10000`
`MAC_Tx_Configuration` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SS` `RW 0x0`			`Reserved_G9991EN` `RO 0x0`	`Reserved_GT9WH` `RO 0x0`	`Reserved_26` `RO 0x0`	`Reserved_VNM` `RO 0x0`	`Reserved_VNE` `RO 0x0`	`Reserved_23` `RO 0x0`	`SARC` `RW 0x0`			`Reserved_PEN` `RO 0x0`	`Reserved_PCHM` `RO 0x0`	`Reserved_17` `RO 0x0`	`JD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`LUD` `RW 0x0`	`TC` `RW 0x0`	`IFP` `RW 0x0`	`IPG` `RW 0x0`			`ISR` `RW 0x0`				`ISM` `RW 0x0`	`Reserved_2` `RO 0x0`	`DDIC` `RW 0x0`	`TE` `RW 0x0`
`MAC_Rx_Configuration` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ARPEN` `RW 0x0`	`Reserved_ELEN` `RO 0x0`	`GPSL` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_PRXM` `RO 0x0`	`HDSMS` `RW 0x0`			`S2KP` `RW 0x0`	`LM` `RW 0x0`	`IPC` `RW 0x0`	`JE` `RW 0x0`	`WD` `RW 0x0`	`GPSLCE` `RW 0x0`	`USP` `RW 0x0`	`SPEN` `RW 0x0`	`DCRCC` `RW 0x0`	`CST` `RW 0x0`	`ACS` `RW 0x0`	`RE` `RW 0x0`
`MAC_Packet_Filter` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RA` `RW 0x0`	`Reserved_30_23` `RO 0x0`								`Reserved_VUCC` `RO 0x0`	`DNTU` `RW 0x0`	`IPFE` `RW 0x0`	`Reserved_19_17` `RO 0x0`			`VTFE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_13` `RO 0x0`			`DHLFRS` `RW 0x0`		`HPF` `RW 0x0`	`SAF` `RW 0x0`	`SAIF` `RW 0x0`	`PCF` `RW 0x0`		`DBF` `RW 0x0`	`PM` `RW 0x0`	`DAIF` `RW 0x0`	`HMC` `RW 0x0`	`HUC` `RW 0x0`	`PR` `RW 0x0`
`MAC_WD_JB_Timeout` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_25` `RO 0x0`							`PJE` `RW 0x0`	`Reserved_23_20` `RO 0x0`				`JTO` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_9` `RO 0x0`							`PWE` `RW 0x0`	`Reserved_7_4` `RO 0x0`				`WTO` `RW 0x0`
`MAC_Hash_Table_Reg0` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`HT31T0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`HT31T0` `RW 0x0`
`MAC_Hash_Table_Reg1` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`HT31T0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`HT31T0` `RW 0x0`
`MAC_VLAN_Tag_Ctrl` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`EIVLRXS` `RW 0x0`	`Reserved_30` `RO 0x0`	`EIVLS` `RW 0x0`		`ERIVLT` `RW 0x0`	`EDVLP` `RW 0x0`	`VTHM` `RW 0x0`	`EVLRXS` `RW 0x0`	`Reserved_23` `RO 0x0`	`EVLS` `RW 0x0`		`DOVLTC` `RW 0x0`	`ERSVLM` `RW 0x0`	`ESVL` `RW 0x0`	`VTIM` `RW 0x0`	`ETV` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_ERIVTL` `RO 0x0`		`Reserved_EROVTL` `RO 0x0`		`Reserved_11_7` `RO 0x0`					`OFS` `RW 0x0`					`CT` `RW 0x0`	`OB` `RW 0x0`
`MAC_VLAN_Tag_Data` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`				`DMACHN` `RW 0x0`			`DMACHEN` `RW 0x0`	`Reserved_23_21` `RO 0x0`			`ERIVLT` `RW 0x0`	`ERSVLM` `RW 0x0`	`DOVLTC` `RW 0x0`	`ETV` `RW 0x0`	`VEN` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`VID` `RW 0x0`
`MAC_VLAN_Hash_Table` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`VLHT` `RW 0x0`
`MAC_VLAN_Incl` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BUSY` `RO 0x0`	`RDWR` `RW 0x0`	`Reserved_29_y` `RO 0x0`			`ADDR` `RW 0x0`			`Reserved_23_22` `RO 0x0`		`CBTI` `RW 0x0`	`VLTI` `RW 0x0`	`CSVL` `RW 0x0`	`VLP` `RW 0x0`	`VLC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`VLT` `RW 0x0`
`MAC_Inner_VLAN_Incl` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_21` `RO 0x0`											`VLTI` `RW 0x0`	`CSVL` `RW 0x0`	`VLP` `RW 0x0`	`VLC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`VLT` `RW 0x0`
`MAC_Rx_Eth_Type_Match` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ET` `RW 0x0`
`MAC_Q0_Tx_Flow_Ctrl` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`DZPQ` `RW 0x0`	`PLT` `RW 0x0`			`Reserved_3_2` `RO 0x0`		`TFE` `RW 0x0`	`FCB` `RW 0x0`
`MAC_Q1_Tx_Flow_Ctrl` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`DZPQ` `RW 0x0`	`PLT` `RW 0x0`			`Reserved_3_2` `RO 0x0`		`TFE` `RW 0x0`	`FCB` `RW 0x0`
`MAC_Q2_Tx_Flow_Ctrl` `0x120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`DZPQ` `RW 0x0`	`PLT` `RW 0x0`			`Reserved_3_2` `RO 0x0`		`TFE` `RW 0x0`	`FCB` `RW 0x0`
`MAC_Q3_Tx_Flow_Ctrl` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`DZPQ` `RW 0x0`	`PLT` `RW 0x0`			`Reserved_3_2` `RO 0x0`		`TFE` `RW 0x0`	`FCB` `RW 0x0`
`MAC_Q4_Tx_Flow_Ctrl` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`DZPQ` `RW 0x0`	`PLT` `RW 0x0`			`Reserved_3_2` `RO 0x0`		`TFE` `RW 0x0`	`FCB` `RW 0x0`
`MAC_Q5_Tx_Flow_Ctrl` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`DZPQ` `RW 0x0`	`PLT` `RW 0x0`			`Reserved_3_2` `RO 0x0`		`TFE` `RW 0x0`	`FCB` `RW 0x0`
`MAC_Q6_Tx_Flow_Ctrl` `0x136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`DZPQ` `RW 0x0`	`PLT` `RW 0x0`			`Reserved_3_2` `RO 0x0`		`TFE` `RW 0x0`	`FCB` `RW 0x0`
`MAC_Q7_Tx_Flow_Ctrl` `0x140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`DZPQ` `RW 0x0`	`PLT` `RW 0x0`			`Reserved_3_2` `RO 0x0`		`TFE` `RW 0x0`	`FCB` `RW 0x0`
`MAC_Rx_Flow_Ctrl` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_9` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_9` `RO 0x0`							`PFCE` `RW 0x0`	`Reserved_7_2` `RO 0x0`						`UP` `RW 0x0`	`RFE` `RW 0x0`
`MAC_RxQ_Ctrl4` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`					`PMCBCQ` `RW 0x0`			`Reserved_23_y` `RO 0x0`				`VFFQ` `RW 0x0`			`VFFQE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_y` `RO 0x0`				`MFFQ` `RW 0x0`			`MFFQE` `RW 0x0`	`Reserved_7_y` `RO 0x0`				`UFFQ` `RW 0x0`			`UFFQE` `RW 0x0`
`MAC_RxQ_Ctrl5` `0x152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`PRQSO` `RW 0x0`
`MAC_RxQ_Ctrl0` `0x160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_RXQ15EN` `RO 0x0`		`Reserved_RXQ14EN` `RO 0x0`		`Reserved_RXQ13EN` `RO 0x0`		`Reserved_RXQ12EN` `RO 0x0`		`Reserved_RXQ11EN` `RO 0x0`		`Reserved_RXQ10EN` `RO 0x0`		`Reserved_RXQ9EN` `RO 0x0`		`Reserved_RXQ8EN` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXQ7EN` `RW 0x0`		`RXQ6EN` `RW 0x0`		`RXQ5EN` `RW 0x0`		`RXQ4EN` `RW 0x0`		`RXQ3EN` `RW 0x0`		`RXQ2EN` `RW 0x0`		`RXQ1EN` `RW 0x0`		`RXQ0EN` `RW 0x0`
`MAC_RxQ_Ctrl1` `0x164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AVCPQ` `RW 0x0`				`PTPQ` `RW 0x0`				`TACPQE` `RW 0x0`	`TPQC` `RW 0x0`		`OMCBCQ` `RW 0x0`	`DCBCPQ` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MCBCQEN` `RW 0x0`	`Reserved_14_12` `RO 0x0`			`MCBCQ` `RW 0x0`				`RQ` `RW 0x0`				`UPQ` `RW 0x0`
`MAC_RxQ_Ctrl2` `0x168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PSRQ3` `RW 0x0`								`PSRQ2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PSRQ1` `RW 0x0`								`PSRQ0` `RW 0x0`
`MAC_RxQ_Ctrl3` `0x172` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PSRQ7` `RW 0x0`								`PSRQ6` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PSRQ5` `RW 0x0`								`PSRQ4` `RW 0x0`
`MAC_Interrupt_Status` `0x176` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_26` `RO 0x0`						`LS` `RO 0x0`		`Reserved_PCIS` `RO 0x0`	`Reserved_22_19` `RO 0x0`				`MFRIS` `RO 0x0`	`MFTIS` `RO 0x0`	`FPEIS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`GPIIS` `RO 0x0`	`RXESIS` `RO 0x0`	`TXESIS` `RO 0x0`	`TSIS` `RO 0x0`	`MMCRXIPIS` `RO 0x0`	`MMCTXIS` `RO 0x0`	`MMCRXIS` `RO 0x0`	`Reserved_8_6` `RO 0x0`			`Reserved_LPIIS` `RO 0x0`	`Reserved_PMTIS` `RO 0x0`	`Reserved_3_2` `RO 0x0`		`SMI` `RO 0x0`	`LSI` `RO 0x0`
`MAC_Interrupt_Enable` `0x180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FPEIE` `RW 0x0`	`RXESIE` `RW 0x0`	`TXESIE` `RW 0x0`	`TSIE` `RW 0x0`	`Reserved_11_6` `RO 0x0`						`Reserved_LPIIE` `RO 0x0`	`Reserved_PMTIE` `RO 0x0`	`Reserved_3_1` `RO 0x0`			`LSIE` `RW 0x1`
`MAC_Rx_Tx_Status` `0x184` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_14` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_14` `RO 0x0`		`PCE` `RO 0x0`	`IHE` `RO 0x0`	`Reserved_11_9` `RO 0x0`			`RWT` `RO 0x0`	`Reserved_7_6` `RO 0x0`		`EXCOL` `RO 0x0`	`LCOL` `RO 0x0`	`EXDEF` `RO 0x0`	`LCARR` `RO 0x0`	`NCARR` `RO 0x0`	`TJT` `RO 0x0`
`MAC_Version` `0x272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_24` `RO 0x0`								`USERVER` `RO 0x10`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DEVID` `RO 0x76`								`SNPSVER` `RO 0x31`
`MAC_Debug` `0x276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_19` `RO 0x0`													`TFCSTS` `RO 0x0`		`TPESTS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_3` `RO 0x0`													`RFCFCSTS` `RO 0x0`		`RPESTS` `RO 0x0`
`MAC_HW_Feature0` `0x284` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`EDMA` `RO 0x1`	`EDIFFC` `RO 0x1`	`VXN` `RO 0x0`	`Reserved_28` `RO 0x0`	`SAVLANINS` `RO 0x1`	`TSSTSSEL` `RO 0x1`		`PHYSEL` `RO 0x0`		`ADDMACADRSEL` `RO 0x1F`					`Reserved_17` `RO 0x0`	`RXCOESEL` `RO 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15` `RO 0x0`	`TXCOESEL` `RO 0x1`	`EEESEL` `RO 0x0`	`TSSEL` `RO 0x1`	`AVSEL` `RO 0x1`	`RAVSEL` `RO 0x0`	`ARPOFFSEL` `RO 0x1`	`MMCSEL` `RO 0x1`	`MGKSEL` `RO 0x0`	`RWKSEL` `RO 0x0`	`SMASEL` `RO 0x1`	`VLHASH` `RO 0x1`	`HDSEL` `RO 0x1`	`RMIISEL` `RO 0x1`	`GMIISEL` `RO 0x1`	`RGMIISEL` `RO 0x1`
`MAC_HW_Feature1` `0x288` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31` `RO 0x0`	`L3L4FNUM` `RO 0x9`				`HASHTBLSZ` `RO 0x1`			`NUMTC` `RO 0x7`			`RSSEN` `RO 0x0`	`DBGMEMA` `RO 0x1`	`TSOEN` `RO 0x1`	`SPHEN` `RO 0x1`	`DCBEN` `RO 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDR64` `RO 0x1`		`ADVTHWORD` `RO 0x1`	`PTOEN` `RO 0x1`	`OSTEN` `RO 0x1`	`TXFIFOSIZE` `RO 0x8`					`PFCEN` `RO 0x1`	`RXFIFOSIZE` `RO 0x7`
`MAC_HW_Feature2` `0x292` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31` `RO 0x0`	`AUXSNAPNUM` `RO 0x2`			`Reserved_27` `RO 0x0`	`PPSOUTNUM` `RO 0x2`			`Reserved_23_22` `RO 0x0`		`TXCHCNT` `RO 0x7`				`Reserved_17_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXCHCNT` `RO 0x7`				`Reserved_11_10` `RO 0x0`		`TXQCNT` `RO 0x7`				`Reserved_5_4` `RO 0x0`		`RXQCNT` `RO 0x7`
`MAC_HW_Feature3` `0x296` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TBS_CH` `RO 0x1`				`TBSSEL` `RO 0x1`	`FPESEL` `RO 0x1`	`SGFSEL` `RO 0x0`	`GCLWID` `RO 0x3`		`GCLDEP` `RO 0x3`			`ESTSEL` `RO 0x1`	`TTSFD` `RO 0x5`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ASP` `RO 0x0`		`DVLAN` `RO 0x1`	`FRPES` `RO 0x0`		`FRPPB` `RO 0x0`		`POUOST` `RO 0x1`	`FRPPIPE` `RO 0x0`			`CBTISEL` `RO 0x1`	`FRPSEL` `RO 0x0`	`NRVF` `RO 0x5`
`MAC_HW_Feature4` `0x300` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_2` `RO 0x0`														`PCSEL` `RO 0x0`
`MAC_Extended_Configuration` `0x320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_25` `RO 0x0`							`HD` `RW 0x0`	`ECRSFD` `RW 0x0`	`DO` `RW 0x0`	`DCRS` `RW 0x0`	`DR` `RW 0x0`	`BL` `RW 0x0`		`DC` `RW 0x0`	`Reserved_SBDIOEN` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_10` `RO 0x0`						`TPRE` `RW 0x0`	`Reserved_VPRE` `RO 0x0`	`DDS` `RW 0x0`	`EIPG` `RW 0x0`
`MAC_Ext_Cfg1` `0x324` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_25` `RO 0x0`							`SAVE` `RW 0x0`	`Reserved_23` `RO 0x0`	`SAVO` `RW 0x2`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_10` `RO 0x0`						`SPLM` `RW 0x0`		`Reserved_7` `RO 0x0`	`SPLOFST` `RW 0x2`
`MDIO_Single_Command_Address` `0x512` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_26` `RO 0x0`						`DA` `RW 0x0`					`PA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RA` `RW 0x0`
`MDIO_Single_Command_Control_Data` `0x516` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRS` `RW 0x0`	`PSE` `RW 0x0`	`Reserved_29_23` `RO 0x0`							`SBusy` `RW 0x0`	`CR` `RW 0x0`			`SAADR` `RW 0x0`	`CMD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SDATA` `RW 0x0`
`MDIO_Continuous_Write_Address` `0x520` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_23` `RO 0x0`									`CBUSY` `RW 0x0`	`CPRT` `RW 0x0`	`CADDR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CREGADDR` `RW 0x0`
`MDIO_Continuous_Write_Data` `0x524` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CDATA` `RW 0x0`
`MDIO_Continuous_Scan_Port_Enable` `0x528` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PORT31SCE` `RW 0x0`	`PORT30SCE` `RW 0x0`	`PORT29SCE` `RW 0x0`	`PORT28SCE` `RW 0x0`	`PORT27SCE` `RW 0x0`	`PORT26SCE` `RW 0x0`	`PORT25SCE` `RW 0x0`	`PORT24SCE` `RW 0x0`	`PORT23SCE` `RW 0x0`	`PORT22SCE` `RW 0x0`	`PORT21SCE` `RW 0x0`	`PORT20SCE` `RW 0x0`	`PORT19SCE` `RW 0x0`	`PORT18SCE` `RW 0x0`	`PORT17SCE` `RW 0x0`	`PORT16SCE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PORT15SCE` `RW 0x0`	`PORT14SCE` `RW 0x0`	`PORT13SCE` `RW 0x0`	`PORT12SCE` `RW 0x0`	`PORT11SCE` `RW 0x0`	`PORT10SCE` `RW 0x0`	`PORT9SCE` `RW 0x0`	`PORT8SCE` `RW 0x0`	`PORT7SCE` `RW 0x0`	`PORT6SCE` `RW 0x0`	`PORT5SCE` `RW 0x0`	`PORT4SCE` `RW 0x0`	`PORT3SCE` `RW 0x0`	`PORT2SCE` `RW 0x0`	`PORT1SCE` `RW 0x0`	`PORT0SCE` `RW 0x0`
`MDIO_Interrupt_Status` `0x532` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_14` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_14` `RO 0x0`		`CWCOMPINT` `RO 0x0`	`SNGLCOMPINT` `RO 0x0`	`PORTNx4P3ALINT` `RO 0x0`	`PORTNx4P2ALINT` `RO 0x0`	`PORTNx4P1ALINT` `RO 0x0`	`PORTNx4P0ALINT` `RO 0x0`	`PORTNx4P3LSINT` `RO 0x0`	`PORTNx4P2LSINT` `RO 0x0`	`PORTNx4P1LSINT` `RO 0x0`	`PORTNx4P0LSINT` `RO 0x0`	`PORTNx4P3CONINT` `RO 0x0`	`PORTNx4P2CONINT` `RO 0x0`	`PORTNx4P1CONINT` `RO 0x0`	`PORTNx4P0CONINT` `RO 0x0`
`MDIO_Interrupt_Enable` `0x536` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_14` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_14` `RO 0x0`		`CWCOMPIE` `RW 0x0`	`SNGLCOMPIE` `RW 0x0`	`PTRNx4P3ALIE` `RW 0x0`	`PTRNx4P2ALIE` `RW 0x0`	`PTRNx4P1ALIE` `RW 0x0`	`PTRNx4P0ALIE` `RW 0x0`	`PTRNx4P3LSIE` `RW 0x0`	`PTRNx4P2LSIE` `RW 0x0`	`PTRNx4P1LSIE` `RW 0x0`	`PTRNx4P0LSIE` `RW 0x0`	`PTRNx4P3CONIE` `RW 0x0`	`PTRNx4P2CONIE` `RW 0x0`	`PTRNx4P1CONIE` `RW 0x0`	`PTRNx4P0CONIE` `RW 0x0`
`MDIO_Port_Connect_Disconnect_Status` `0x540` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PORT31CON` `RO 0x0`	`PORT30CON` `RO 0x0`	`PORT29CON` `RO 0x0`	`PORT28CON` `RO 0x0`	`PORT27CON` `RO 0x0`	`PORT26CON` `RO 0x0`	`PORT25CON` `RO 0x0`	`PORT24CON` `RO 0x0`	`PORT23CON` `RO 0x0`	`PORT22CON` `RO 0x0`	`PORT21CON` `RO 0x0`	`PORT20CON` `RO 0x0`	`PORT19CON` `RO 0x0`	`PORT18CON` `RO 0x0`	`PORT17CON` `RO 0x0`	`PORT16CON` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PORT15CON` `RO 0x0`	`PORT14CON` `RO 0x0`	`PORT13CON` `RO 0x0`	`PORT12CON` `RO 0x0`	`PORT11CON` `RO 0x0`	`PORT10CON` `RO 0x0`	`PORT9CON` `RO 0x0`	`PORT8CON` `RO 0x0`	`PORT7CON` `RO 0x0`	`PORT6CON` `RO 0x0`	`PORT5CON` `RO 0x0`	`PORT4CON` `RO 0x0`	`PORT3CON` `RO 0x0`	`PORT2CON` `RO 0x0`	`PORT1CON` `RO 0x0`	`PORT0CON` `RO 0x0`
`MDIO_Clause_22_Port` `0x544` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PTR31CL22` `RW 0x0`	`PTR30CL22` `RW 0x0`	`PTR29CL22` `RW 0x0`	`PTR28CL22` `RW 0x0`	`PTR27CL22` `RW 0x0`	`PTR26CL22` `RW 0x0`	`PTR25CL22` `RW 0x0`	`PTR24CL22` `RW 0x0`	`PTR23CL22` `RW 0x0`	`PTR22CL22` `RW 0x0`	`PTR21CL22` `RW 0x0`	`PTR20CL22` `RW 0x0`	`PTR19CL22` `RW 0x0`	`PTR18CL22` `RW 0x0`	`PTR17CL22` `RW 0x0`	`PTR16CL22` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PTR15CL22` `RW 0x0`	`PTR14CL22` `RW 0x0`	`PTR13CL22` `RW 0x0`	`PTR12CL22` `RW 0x0`	`PTR11CL22` `RW 0x0`	`PTR10CL22` `RW 0x0`	`PTR9CL22` `RW 0x0`	`PTR8CL22` `RW 0x0`	`PTR7CL22` `RW 0x0`	`PTR6CL22` `RW 0x0`	`PTR5CL22` `RW 0x0`	`PTR4CL22` `RW 0x0`	`PTR3CL22` `RW 0x0`	`PTR2CL22` `RW 0x0`	`PTR1CL22` `RW 0x0`	`PTR0CL22` `RW 0x0`
`MDIO_Port_Nx4_Indirect_Control` `0x548` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`PRS` `RW 0x0`
`MDIO_PortNx4P0_Device_In_Use` `0x560` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P0VSD2` `RW 0x1`	`Nx4P0VSD1` `RW 0x1`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P0TC` `RW 0x1`	`Nx4P0DTEXS` `RW 0x1`	`Nx4P0PHYXS` `RW 0x1`	`Nx4P0PCS` `RW 0x1`	`Nx4P0WIS` `RW 0x1`	`Nx4P0PMDPMA` `RW 0x1`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P0_Link_Status` `0x564` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P0VSD2LS` `RO 0x0`	`Nx4P0VSD1LS` `RO 0x0`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P0TCLS` `RO 0x0`	`Nx4P0DTEXSLS` `RO 0x0`	`Nx4P0PHYXSLS` `RO 0x0`	`Nx4P0PCSLS` `RO 0x0`	`Nx4P0WISLS` `RO 0x0`	`Nx4P0PMDPMALS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P0_Alive_Status` `0x568` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P0VSD2LS` `RO 0x0`	`Nx4P0VSD1LS` `RO 0x0`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P0TCLS` `RO 0x0`	`Nx4P0DTEXSLS` `RO 0x0`	`Nx4P0PHYXSLS` `RO 0x0`	`Nx4P0PCSLS` `RO 0x0`	`Nx4P0WISLS` `RO 0x0`	`Nx4P0PMDPMALS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P1_Device_In_Use` `0x576` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P1VSD2` `RW 0x1`	`Nx4P1VSD1` `RW 0x1`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P1TC` `RW 0x1`	`Nx4P1DTEXS` `RW 0x1`	`Nx4P1PHYXS` `RW 0x1`	`Nx4P1PCS` `RW 0x1`	`Nx4P1WIS` `RW 0x1`	`Nx4P1PMDPMA` `RW 0x1`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P1_Link_Status` `0x580` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P1VSD2LS` `RO 0x0`	`Nx4P1VSD1LS` `RO 0x0`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P1TCLS` `RO 0x0`	`Nx4P1DTEXSLS` `RO 0x0`	`Nx4P1PHYXSLS` `RO 0x0`	`Nx4P1PCSLS` `RO 0x0`	`Nx4P1WISLS` `RO 0x0`	`Nx4P1PMDPMALS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P1_Alive_Status` `0x584` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P1VSD2LS` `RO 0x0`	`Nx4P1VSD1LS` `RO 0x0`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P1TCLS` `RO 0x0`	`Nx4P1DTEXSLS` `RO 0x0`	`Nx4P1PHYXSLS` `RO 0x0`	`Nx4P1PCSLS` `RO 0x0`	`Nx4P1WISLS` `RO 0x0`	`Nx4P1PMDPMALS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P2_Device_In_Use` `0x592` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P2VSD2` `RW 0x1`	`Nx4P2VSD1` `RW 0x1`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P2TC` `RW 0x1`	`Nx4P2DTEXS` `RW 0x1`	`Nx4P2PHYXS` `RW 0x1`	`Nx4P2PCS` `RW 0x1`	`Nx4P2WIS` `RW 0x1`	`Nx4P2PMDPMA` `RW 0x1`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P2_Link_Status` `0x596` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P2VSD2LS` `RO 0x0`	`Nx4P2VSD1LS` `RO 0x0`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P2TCLS` `RO 0x0`	`Nx4P2DTEXSLS` `RO 0x0`	`Nx4P2PHYXSLS` `RO 0x0`	`Nx4P2PCSLS` `RO 0x0`	`Nx4P2WISLS` `RO 0x0`	`Nx4P2PMDPMALS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P2_Alive_Status` `0x600` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P2VSD2LS` `RO 0x0`	`Nx4P2VSD1LS` `RO 0x0`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P2TCLS` `RO 0x0`	`Nx4P2DTEXSLS` `RO 0x0`	`Nx4P2PHYXSLS` `RO 0x0`	`Nx4P2PCSLS` `RO 0x0`	`Nx4P2WISLS` `RO 0x0`	`Nx4P2PMDPMALS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P3_Device_In_Use` `0x608` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P3VSD2` `RW 0x1`	`Nx4P3VSD1` `RW 0x1`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P3TC` `RW 0x1`	`Nx4P3DTEXS` `RW 0x1`	`Nx4P3PHYXS` `RW 0x1`	`Nx4P3PCS` `RW 0x1`	`Nx4P3WIS` `RW 0x1`	`Nx4P3PMDPMA` `RW 0x1`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P3_Link_Status` `0x612` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P3VSD2LS` `RO 0x0`	`Nx4P3VSD1LS` `RO 0x0`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P3TCLS` `RO 0x0`	`Nx4P3DTEXSLS` `RO 0x0`	`Nx4P3PHYXSLS` `RO 0x0`	`Nx4P3PCSLS` `RO 0x0`	`Nx4P3WISLS` `RO 0x0`	`Nx4P3PMDPMALS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MDIO_PortNx4P3_Alive_Status` `0x616` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Nx4P3VSD2LS` `RO 0x0`	`Nx4P3VSD1LS` `RO 0x0`	`Reserved_29_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_29_7` `RO 0x0`									`Nx4P3TCLS` `RO 0x0`	`Nx4P3DTEXSLS` `RO 0x0`	`Nx4P3PHYXSLS` `RO 0x0`	`Nx4P3PCSLS` `RO 0x0`	`Nx4P3WISLS` `RO 0x0`	`Nx4P3PMDPMALS` `RO 0x0`	`Reserved_0` `RO 0x0`
`MAC_GPIO_Control` `0x632` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`								`GPIT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_4` `RO 0x0`												`GPIE` `RW 0x0`
`MAC_GPIO_Status` `0x636` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_y` `RO 0x0`								`GPO` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_y` `RO 0x0`								`GPIS` `RO 0x0`
`MAC_FPE_CTRL_STS` `0x640` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_20` `RO 0x0`												`TRSP` `RO 0x0`	`TVER` `RO 0x0`	`RRSP` `RO 0x0`	`RVER` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_4` `RO 0x0`												`ARV` `RW 0x0`	`SRSP` `RW 0x0`	`SVER` `RW 0x0`	`EFPE` `RW 0x0`
`MAC_CSR_SW_Ctrl` `0x656` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_9` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_9` `RO 0x0`							`SEEN` `RW 0x0`	`Reserved_7_1` `RO 0x0`							`RCWE` `RW 0x0`
`MAC_Address0_High` `0x768` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RO 0x1`	`Reserved_30_y` `RO 0x0`												`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address0_Low` `0x772` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address1_High` `0x776` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address1_Low` `0x780` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address2_High` `0x784` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address2_Low` `0x788` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address3_High` `0x792` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address3_Low` `0x796` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address4_High` `0x800` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address4_Low` `0x804` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address5_High` `0x808` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address5_Low` `0x812` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address6_High` `0x816` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address6_Low` `0x820` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address7_High` `0x824` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address7_Low` `0x828` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address8_High` `0x832` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address8_Low` `0x836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address9_High` `0x840` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address9_Low` `0x844` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address10_High` `0x848` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address10_Low` `0x852` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address11_High` `0x856` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address11_Low` `0x860` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address12_High` `0x864` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address12_Low` `0x868` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address13_High` `0x872` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address13_Low` `0x876` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address14_High` `0x880` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address14_Low` `0x884` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address15_High` `0x888` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address15_Low` `0x892` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address16_High` `0x896` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address16_Low` `0x900` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address17_High` `0x904` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address17_Low` `0x908` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address18_High` `0x912` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address18_Low` `0x916` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address19_High` `0x920` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address19_Low` `0x924` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address20_High` `0x928` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address20_Low` `0x932` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address21_High` `0x936` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address21_Low` `0x940` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address22_High` `0x944` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address22_Low` `0x948` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address23_High` `0x952` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address23_Low` `0x956` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address24_High` `0x960` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address24_Low` `0x964` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address25_High` `0x968` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address25_Low` `0x972` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address26_High` `0x976` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address26_Low` `0x980` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address27_High` `0x984` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address27_Low` `0x988` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address28_High` `0x992` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address28_Low` `0x996` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address29_High` `0x1000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address29_Low` `0x1004` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address30_High` `0x1008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address30_Low` `0x1012` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Address31_High` `0x1016` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AE` `RW 0x0`	`SA` `RW 0x0`	`MBC` `RW 0x0`						`Reserved_23_y` `RO 0x0`					`DCS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRHI` `RW 0xFFFF`
`MAC_Address31_Low` `0x1020` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDRLO` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ADDRLO` `RW 0xFFFFFFFF`
`MAC_Indir_Access_Ctrl` `0x1792` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SNPS_R` `RW 0x0`	`Reserved_30` `RO 0x0`	`MSEL` `RW 0x0`				`Reserved_25_24` `RO 0x0`		`Reserved_23_x` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AOFF` `RW 0x0`								`Reserved_7_6` `RO 0x0`		`AUTO` `RW 0x0`	`Reserved_4_2` `RO 0x0`			`COM` `RW 0x0`	`OB` `RW 0x0`
`MAC_Indir_Access_Data` `0x1796` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DATA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DATA` `RW 0x0`
`MMC_Control` `0x2048` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_19` `RO 0x0`													`Reserved_PRMMCSEL` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_8` `RO 0x0`								`CNTPRST` `RW 0x0`	`Reserved_6` `RO 0x0`	`MCT` `RW 0x2`		`MCF` `RW 0x0`	`RSTONRD` `RW 0x0`	`CNTSTOPRO` `RW 0x0`	`CNTRST` `RW 0x0`
`MMC_Rx_Interrupt` `0x2052` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXPRMMCIS` `RO 0x0`	`Reserved_30` `RO 0x0`	`SGFPIS` `RO 0x0`	`SGPPIS` `RO 0x0`	`RXALEPIS` `RO 0x0`	`RXLPITRCIS` `RO 0x0`	`RXLPIUSCIS` `RO 0x0`	`RXDISOCGBIS` `RO 0x0`	`RXDISPCGBIS` `RO 0x0`	`RXWDOGPIS` `RO 0x0`	`RXVLANGBPIS` `RO 0x0`	`RXFOVPIS` `RO 0x0`	`RXPAUSPIS` `RO 0x0`	`RXORANGEPIS` `RO 0x0`	`RXLENERPIS` `RO 0x0`	`RXUCGPIS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RX1024TMAXOCTGBPIS` `RO 0x0`	`RX512T1023OCTGBPIS` `RO 0x0`	`RX256T511OCTGBPIS` `RO 0x0`	`RX128T255OCTGBPIS` `RO 0x0`	`RX65T127OCTGBPIS` `RO 0x0`	`RX64OCTGBPIS` `RO 0x0`	`RXOSIZEGPIS` `RO 0x0`	`RXUSIZEGPIS` `RO 0x0`	`RXJABERPIS` `RO 0x0`	`RXRUNTPIS` `RO 0x0`	`RXCRCERPIS` `RO 0x0`	`RXMCGPIS` `RO 0x0`	`RXBCGPIS` `RO 0x0`	`RXGOCTIS` `RO 0x0`	`RXGBOCTIS` `RO 0x0`	`RXGBPKTIS` `RO 0x0`
`MMC_Tx_Interrupt` `0x2056` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXPRMMCIS` `RO 0x0`	`Reserved_30_27` `RO 0x0`				`TXEXDEFPIS` `RO 0x0`	`TXCARERPIS` `RO 0x0`	`TXEXCOLPIS` `RO 0x0`	`TXLATCOLPIS` `RO 0x0`	`TXDEFPIS` `RO 0x0`	`TXMCOLGPIS` `RO 0x0`	`TXSCOLGPIS` `RO 0x0`	`TXLPITRCIS` `RO 0x0`	`TXLPIUSCIS` `RO 0x0`	`TXVLANGPIS` `RO 0x0`	`TXPAUSPIS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXGPKTIS` `RO 0x0`	`TXGOCTIS` `RO 0x0`	`TXUFLOWERPIS` `RO 0x0`	`TXBCGBPIS` `RO 0x0`	`TXMCGBPIS` `RO 0x0`	`TXUCGBPIS` `RO 0x0`	`TX1024TMAXOCTGBPIS` `RO 0x0`	`TX512T1023OCTGBPIS` `RO 0x0`	`TX256T511OCTGBPIS` `RO 0x0`	`TX128T255OCTGBPIS` `RO 0x0`	`TX65T127OCTGBPIS` `RO 0x0`	`TX64OCTGBPIS` `RO 0x0`	`TXMCGPIS` `RO 0x0`	`TXBCGPIS` `RO 0x0`	`TXGBPKTIS` `RO 0x0`	`TXGBOCTIS` `RO 0x0`
`MMC_Receive_Interrupt_Enable` `0x2060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_RXPRMMCIE` `RO 0x0`	`Reserved_30` `RO 0x0`	`Reserved_SGFPIE` `RO 0x0`	`Reserved_SGPPIE` `RO 0x0`	`RXALEPIE` `RW 0x0`	`Reserved_RXLPITRCIE` `RO 0x0`	`Reserved_RXLPIUSCIE` `RO 0x0`	`RXDISOCGBIE` `RW 0x0`	`RXDISPCGBIE` `RW 0x0`	`RXWDOGPIE` `RW 0x0`	`RXVLANGBPIE` `RW 0x0`	`RXFOVPIE` `RW 0x0`	`RXPAUSPIE` `RW 0x0`	`RXORANGEPIE` `RW 0x0`	`RXLENERPIE` `RW 0x0`	`RXUCGPIE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RX1024TMAXOCTGBPIE` `RW 0x0`	`RX512T1023OCTGBPIE` `RW 0x0`	`RX256T511OCTGBPIE` `RW 0x0`	`RX128T255OCTGBPIE` `RW 0x0`	`RX65T127OCTGBPIE` `RW 0x0`	`RX64OCTGBPIE` `RW 0x0`	`RXOSIZEGPIE` `RW 0x0`	`RXUSIZEGPIE` `RW 0x0`	`RXJABERPIE` `RW 0x0`	`RXRUNTPIE` `RW 0x0`	`RXCRCERPIE` `RW 0x0`	`RXMCGPIE` `RW 0x0`	`RXBCGPIE` `RW 0x0`	`RXGOCTIE` `RW 0x0`	`RXGBOCTIE` `RW 0x0`	`RXGBPKTIE` `RW 0x0`
`MMC_Transmit_Interrupt_Enable` `0x2064` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_TXPRMMCIE` `RO 0x0`	`Reserved_30_27` `RO 0x0`				`TXEXDEFPIE` `RW 0x0`	`TXCARERPIE` `RW 0x0`	`TXEXCOLPIE` `RW 0x0`	`TXLATCOLPIE` `RW 0x0`	`TXDEFPIE` `RW 0x0`	`TXMCOLGPIE` `RW 0x0`	`TXSCOLGPIE` `RW 0x0`	`Reserved_TXLPITRCIE` `RO 0x0`	`Reserved_TXLPIUSCIE` `RO 0x0`	`TXVLANGPIE` `RW 0x0`	`TXPAUSPIE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXGPKTIE` `RW 0x0`	`TXGOCTIE` `RW 0x0`	`TXUFLOWERPIE` `RW 0x0`	`TXBCGBPIE` `RW 0x0`	`TXMCGBPIE` `RW 0x0`	`TXUCGBPIE` `RW 0x0`	`TX1024TMAXOCTGBPIE` `RW 0x0`	`TX512T1023OCTGBPIE` `RW 0x0`	`TX256T511OCTGBPIE` `RW 0x0`	`TX128T255OCTGBPIE` `RW 0x0`	`TX65T127OCTGBPIE` `RW 0x0`	`TX64OCTGBPIE` `RW 0x0`	`TXMCGPIE` `RW 0x0`	`TXBCGPIE` `RW 0x0`	`TXGBPKTIE` `RW 0x0`	`TXGBOCTIE` `RW 0x0`
`Tx_Octet_Count_Good_Bad_Low` `0x2068` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXOCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXOCTGBLO` `RO 0x0`
`Tx_Octet_Count_Good_Bad_High` `0x2072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXOCTGBHI` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXOCTGBHI` `RO 0x0`
`Tx_Packet_Count_Good_Bad_Low` `0x2076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXPKTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXPKTGBLO` `RO 0x0`
`Tx_Broadcast_Packets_Good_Low` `0x2084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXBCASTGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXBCASTGLO` `RO 0x0`
`Tx_Multicast_Packets_Good_Low` `0x2092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXMCASTGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXMCASTGLO` `RO 0x0`
`Tx_64Octets_Packets_Good_Bad_Low` `0x2100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TX64OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TX64OCTGBLO` `RO 0x0`
`Tx_65To127Octets_Packets_Good_Bad_Low` `0x2108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TX65_127OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TX65_127OCTGBLO` `RO 0x0`
`Tx_128To255Octets_Packets_Good_Bad_Low` `0x2116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TX128_255OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TX128_255OCTGBLO` `RO 0x0`
`Tx_256To511Octets_Packets_Good_Bad_Low` `0x2124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TX256_511OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TX256_511OCTGBLO` `RO 0x0`
`Tx_512To1023Octets_Packets_Good_Bad_Low` `0x2132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TX512_1023OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TX512_1023OCTGBLO` `RO 0x0`
`Tx_1024ToMaxOctets_Packets_Good_Bad_Low` `0x2140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TX1024_MAXOCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TX1024_MAXOCTGBLO` `RO 0x0`
`Tx_Unicast_Packets_Good_Bad_Low` `0x2148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXUCASTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXUCASTGBLO` `RO 0x0`
`Tx_Multicast_Packets_Good_Bad_Low` `0x2156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXMCASTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXMCASTGBLO` `RO 0x0`
`Tx_Broadcast_Packets_Good_Bad_Low` `0x2164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXBCASTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXBCASTGBLO` `RO 0x0`
`Tx_Underflow_Error_Packets_Low` `0x2172` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXUNDRFLWLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXUNDRFLWLO` `RO 0x0`
`Tx_Octet_Count_Good_Low` `0x2180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXOCTGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXOCTGLO` `RO 0x0`
`Tx_Octet_Count_Good_High` `0x2184` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXOCTGHI` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXOCTGHI` `RO 0x0`
`Tx_Packet_Count_Good_Low` `0x2188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXPKTGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXPKTGLO` `RO 0x0`
`Tx_Pause_Packets_Low` `0x2196` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXPAUSEGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXPAUSEGLO` `RO 0x0`
`Tx_VLAN_Packets_Good_Low` `0x2204` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXVLANGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXVLANGLO` `RO 0x0`
`Rx_Packet_Count_Good_Bad_Low` `0x2304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXPKTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXPKTGBLO` `RO 0x0`
`Rx_Octet_Count_Good_Bad_Low` `0x2312` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXOCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXOCTGBLO` `RO 0x0`
`Rx_Octet_Count_Good_Bad_High` `0x2316` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXOCTGBHI` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXOCTGBHI` `RO 0x0`
`Rx_Octet_Count_Good_Low` `0x2320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXOCTGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXOCTGLO` `RO 0x0`
`Rx_Octet_Count_Good_High` `0x2324` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXOCTGHI` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXOCTGHI` `RO 0x0`
`Rx_Broadcast_Packets_Good_Low` `0x2328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXBCASTGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXBCASTGLO` `RO 0x0`
`Rx_Multicast_Packets_Good_Low` `0x2336` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXMCASTGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXMCASTGLO` `RO 0x0`
`Rx_CRC_Error_Packets_Low` `0x2344` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXCRCERLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXCRCERLO` `RO 0x0`
`Rx_Runt_Error_Packets` `0x2352` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXRUNTER` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXRUNTER` `RO 0x0`
`Rx_Jabber_Error_Packets` `0x2356` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXJABERER` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXJABERER` `RO 0x0`
`Rx_Undersize_Packets_Good` `0x2360` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXUSIZEG` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXUSIZEG` `RO 0x0`
`Rx_Oversize_Packets_Good` `0x2364` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXOSIZEG` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXOSIZEG` `RO 0x0`
`Rx_64Octets_Packets_Good_Bad_Low` `0x2368` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RX64OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RX64OCTGBLO` `RO 0x0`
`Rx_65To127Octets_Packets_Good_Bad_Low` `0x2376` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RX65_127OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RX65_127OCTGBLO` `RO 0x0`
`Rx_128To255Octets_Packets_Good_Bad_Low` `0x2384` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RX128_255OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RX128_255OCTGBLO` `RO 0x0`
`Rx_256To511Octets_Packets_Good_Bad_Low` `0x2392` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RX256_511OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RX256_511OCTGBLO` `RO 0x0`
`Rx_512To1023Octets_Packets_Good_Bad_Low` `0x2400` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RX512_1023OCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RX512_1023OCTGBLO` `RO 0x0`
`Rx_1024ToMaxOctets_Packets_Good_Bad_Low` `0x2408` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RX1024_MAXOCTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RX1024_MAXOCTGBLO` `RO 0x0`
`Rx_Unicast_Packets_Good_Low` `0x2416` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXUCASTGLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXUCASTGLO` `RO 0x0`
`Rx_Length_Error_Packets_Low` `0x2424` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXLENERRLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXLENERRLO` `RO 0x0`
`Rx_OutofRange_Packets_Low` `0x2432` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXORANGELO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXORANGELO` `RO 0x0`
`Rx_Pause_Packets_Low` `0x2440` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXPAUSELO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXPAUSELO` `RO 0x0`
`Rx_FIFOOverflow_Packets_Low` `0x2448` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXFOVFLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXFOVFLO` `RO 0x0`
`Rx_VLAN_Packets_Good_Bad_Low` `0x2456` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXVLANGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXVLANGBLO` `RO 0x0`
`Rx_Watchdog_Error_Packets` `0x2464` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXWDOGERR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXWDOGERR` `RO 0x0`
`Rx_Discard_Packets_Good_Bad_Low` `0x2476` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXDPCNTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXDPCNTGBLO` `RO 0x0`
`Rx_Discard_Octets_Good_Bad_Low` `0x2484` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXDOCNTGBLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXDOCNTGBLO` `RO 0x0`
`Rx_Discard_Octets_Good_Bad_High` `0x2488` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXDOCNTGBHI` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXDOCNTGBHI` `RO 0x0`
`Rx_Alignment_Error_Packets` `0x2492` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXALIGNERR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXALIGNERR` `RO 0x0`
`MMC_FPE_Tx_Interrupt` `0x2560` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`GOCIS` `RO 0x0`	`HRCIS` `RO 0x0`	`FCIS` `RO 0x0`
`MMC_FPE_Tx_Interrupt_Mask` `0x2564` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_3` `RO 0x0`													`GOCIM` `RW 0x0`	`HRCIM` `RW 0x0`	`FCIM` `RW 0x0`
`MMC_Tx_FPE_Fragment_Cntr` `0x2568` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXFFC` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXFFC` `RO 0x0`
`MMC_Tx_Hold_Req_Cntr` `0x2572` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXHRC` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXHRC` `RO 0x0`
`MMC_Tx_Gate_Orun_Cntr_Low` `0x2576` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXGOCL` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXGOCL` `RO 0x0`
`MMC_Tx_Gate_Orun_Cntr_High` `0x2580` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXGOCH` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXGOCH` `RO 0x0`
`MMC_FPE_Rx_Interrupt` `0x2592` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`FCIS` `RO 0x0`	`PAOCIS` `RO 0x0`	`PSECIS` `RO 0x0`	`PAECIS` `RO 0x0`
`MMC_FPE_Rx_Interrupt_Mask` `0x2596` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_4` `RO 0x0`												`FCIM` `RW 0x0`	`PAOCIM` `RW 0x0`	`PSECIM` `RW 0x0`	`PAECIM` `RW 0x0`
`MMC_Rx_Packet_Assembly_Err_Cntr` `0x2600` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PAEC` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PAEC` `RO 0x0`
`MMC_Rx_Packet_SMD_Err_Cntr` `0x2604` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PSEC` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PSEC` `RO 0x0`
`MMC_Rx_Packet_Assembly_OK_Cntr` `0x2608` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PAOC` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PAOC` `RO 0x0`
`MMC_Rx_FPE_Fragment_Cntr` `0x2612` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FFC` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FFC` `RO 0x0`
`Tx_Single_Collision_Good_Packets` `0x2624` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXSNGLCOLG` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXSNGLCOLG` `RO 0x0`
`Tx_Multiple_Collision_Good_Packets` `0x2628` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXMULTCOLG` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXMULTCOLG` `RO 0x0`
`Tx_Deferred_Packets` `0x2632` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXDEFRD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXDEFRD` `RO 0x0`
`Tx_Late_Collision_Packets` `0x2636` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXLATECOL` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXLATECOL` `RO 0x0`
`Tx_Excessive_Collision_Packets` `0x2640` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXEXSCOL` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXEXSCOL` `RO 0x0`
`Tx_Carrier_Error_Packets` `0x2644` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXCARR` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXCARR` `RO 0x0`
`Tx_Excessive_Deferral_Error` `0x2648` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXEXSDEF` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXEXSDEF` `RO 0x0`
`MMC_IPC_Rx_Interrupt_Mask` `0x2652` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_30` `RO 0x0`		`RXICMPEROIM` `RW 0x0`	`RXICMPGOIM` `RW 0x0`	`RXTCPEROIM` `RW 0x0`	`RXTCPGOIM` `RW 0x0`	`RXUDPEROIM` `RW 0x0`	`RXUDPGOIM` `RW 0x0`	`RXIPV6NOPAYOIM` `RW 0x0`	`RXIPV6HEROIM` `RW 0x0`	`RXIPV6GOIM` `RW 0x0`	`RXIPV4UDSBLOIM` `RW 0x0`	`RXIPV4FRAGOIM` `RW 0x0`	`RXIPV4NOPAYOIM` `RW 0x0`	`RXIPV4HEROIM` `RW 0x0`	`RXIPV4GOIM` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`RXICMPERPIM` `RW 0x0`	`RXICMPGPIM` `RW 0x0`	`RXTCPERPIM` `RW 0x0`	`RXTCPGPIM` `RW 0x0`	`RXUDPERPIM` `RW 0x0`	`RXUDPGPIM` `RW 0x0`	`RXIPV6NOPAYPIM` `RW 0x0`	`RXIPV6HERPIM` `RW 0x0`	`RXIPV6GPIM` `RW 0x0`	`RXIPV4UDSBLPIM` `RW 0x0`	`RXIPV4FRAGPIM` `RW 0x0`	`RXIPV4NOPAYPIM` `RW 0x0`	`RXIPV4HERPIM` `RW 0x0`	`RXIPV4GPIM` `RW 0x0`
`MMC_IPC_Rx_Interrupt` `0x2656` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_30` `RO 0x0`		`RXICMPEROIS` `RO 0x0`	`RXICMPGOIS` `RO 0x0`	`RXTCPEROIS` `RO 0x0`	`RXTCPGOIS` `RO 0x0`	`RXUDPEROIS` `RO 0x0`	`RXUDPGOIS` `RO 0x0`	`RXIPV6NOPAYOIS` `RO 0x0`	`RXIPV6HEROIS` `RO 0x0`	`RXIPV6GOIS` `RO 0x0`	`RXIPV4UDSBLOIS` `RO 0x0`	`RXIPV4FRAGOIS` `RO 0x0`	`RXIPV4NOPAYOIS` `RO 0x0`	`RXIPV4HEROIS` `RO 0x0`	`RXIPV4GOIS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15_14` `RO 0x0`		`RXICMPERPIS` `RO 0x0`	`RXICMPGPIS` `RO 0x0`	`RXTCPERPIS` `RO 0x0`	`RXTCPGPIS` `RO 0x0`	`RXUDPERPIS` `RO 0x0`	`RXUDPGPIS` `RO 0x0`	`RXIPV6NOPAYPIS` `RO 0x0`	`RXIPV6HERPIS` `RO 0x0`	`RXIPV6GPIS` `RO 0x0`	`RXIPV4UDSBLPIS` `RO 0x0`	`RXIPV4FRAGPIS` `RO 0x0`	`RXIPV4NOPAYPIS` `RO 0x0`	`RXIPV4HERPIS` `RO 0x0`	`RXIPV4GPIS` `RO 0x0`
`RxIPv4_Good_Packets_Low` `0x2660` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4GDPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4GDPKTLO` `RO 0x0`
`RxIPv4_Header_Error_Packets_Low` `0x2668` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4HDRERRPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4HDRERRPKTLO` `RO 0x0`
`RxIPv4_No_Payload_Packets_Low` `0x2676` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4NOPAYPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4NOPAYPKTLO` `RO 0x0`
`RxIPv4_Fragmented_Packets_Low` `0x2684` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4FRAGPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4FRAGPKTLO` `RO 0x0`
`RxIPv4_UDP_Checksum_Disabled_Packets_Low` `0x2692` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4UDSBLPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4UDSBLPKTLO` `RO 0x0`
`RxIPv6_Good_Packets_Low` `0x2700` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV6GDPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV6GDPKTLO` `RO 0x0`
`RxIPv6_Header_Error_Packets_Low` `0x2708` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV6HDRERRPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV6HDRERRPKTLO` `RO 0x0`
`RxIPv6_No_Payload_Packets_Low` `0x2716` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV6NOPAYPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV6NOPAYPKTLO` `RO 0x0`
`RxUDP_Good_Packets_Low` `0x2724` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXUDPGDPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXUDPGDPKTLO` `RO 0x0`
`RxUDP_Error_Packets_Low` `0x2732` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXUDPERRPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXUDPERRPKTLO` `RO 0x0`
`RxTCP_Good_Packets_Low` `0x2740` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXTCPGDPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXTCPGDPKTLO` `RO 0x0`
`RxTCP_Error_Packets_Low` `0x2748` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXTCPERRPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXTCPERRPKTLO` `RO 0x0`
`RxICMP_Good_Packets_Low` `0x2756` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXICMPGDPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXICMPGDPKTLO` `RO 0x0`
`RxICMP_Error_Packets_Low` `0x2764` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXICMPERRPKTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXICMPERRPKTLO` `RO 0x0`
`RxIPv4_Good_Octets_Low` `0x2772` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4GDOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4GDOCTLO` `RO 0x0`
`RxIPv4_Header_Error_Octets_Low` `0x2780` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4HDRERROCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4HDRERROCTLO` `RO 0x0`
`RxIPv4_No_Payload_Octets_Low` `0x2788` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4NOPAYOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4NOPAYOCTLO` `RO 0x0`
`RxIPv4_Fragmented_Octets_Low` `0x2796` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4FRAGOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4FRAGOCTLO` `RO 0x0`
`RxIPv4_UDP_Checksum_Disable_Octets_Low` `0x2804` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV4UDSBLOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV4UDSBLOCTLO` `RO 0x0`
`RxIPv6_Good_Octets_Low` `0x2812` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV6GDOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV6GDOCTLO` `RO 0x0`
`RxIPv6_Header_Error_Octets_Low` `0x2820` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV6HDRERROCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV6HDRERROCTLO` `RO 0x0`
`RxIPv6_No_Payload_Octets_Low` `0x2828` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXIPV6NOPAYOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXIPV6NOPAYOCTLO` `RO 0x0`
`RxUDP_Good_Octets_Low` `0x2836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXUDPGDOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXUDPGDOCTLO` `RO 0x0`
`RxUDP_Error_Octets_Low` `0x2844` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXUDPERROCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXUDPERROCTLO` `RO 0x0`
`RxTCP_Good_Octets_Low` `0x2852` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXTCPGDOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXTCPGDOCTLO` `RO 0x0`
`RxTCP_Error_Octets_Low` `0x2860` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXTCPERROCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXTCPERROCTLO` `RO 0x0`
`RxICMP_Good_Octets_Low` `0x2868` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXICMPGDOCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXICMPGDOCTLO` `RO 0x0`
`RxICMP_Error_Octets_Low` `0x2876` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RXICMPERROCTLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RXICMPERROCTLO` `RO 0x0`
`MAC_L3_L4_Address_Control` `0x3072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`IDDR` `RW 0x0`								`Reserved_7_2` `RO 0x0`						`TT` `RW 0x0`	`XB` `RW 0x0`
`MAC_L3_L4_Data` `0x3076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`IDATA` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`IDATA` `RW 0x0`
`MAC_ARP_Address` `0x3088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ARPPA` `RW 0xFFFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ARPPA` `RW 0xFFFFFFFF`
`MAC_Timestamp_Control` `0x3328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_29` `RO 0x0`			`AV8021ASMEN` `RW 0x0`	`Reserved_27_25` `RO 0x0`			`TXTSSTSM` `RW 0x0`	`Reserved_23_21` `RO 0x0`			`Reserved_ESTI` `RO 0x0`	`CSC` `RW 0x0`	`TSENMACADDR` `RW 0x0`	`SNAPTYPSEL` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSMSTRENA` `RW 0x0`	`TSEVNTENA` `RW 0x0`	`TSIPV4ENA` `RW 0x1`	`TSIPV6ENA` `RW 0x0`	`TSIPENA` `RW 0x0`	`TSVER2ENA` `RW 0x0`	`TSCTRLSSR` `RW 0x0`	`TSENALL` `RW 0x0`	`Reserved_7_6` `RO 0x0`		`TSADDREG` `RW 0x0`	`Reserved_TSTRIG` `RO 0x0`	`TSUPDT` `RW 0x0`	`TSINIT` `RW 0x0`	`TSCFUPDT` `RW 0x0`	`TSENA` `RW 0x0`
`MAC_Sub_Second_Increment` `0x3332` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_24` `RO 0x0`								`SSINC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SNSINC` `RW 0x0`								`Reserved_7_0` `RO 0x0`
`MAC_System_Time_Seconds` `0x3336` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TSS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSS` `RO 0x0`
`MAC_System_Time_Nanoseconds` `0x3340` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31` `RO 0x0`	`TSSS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSSS` `RO 0x0`
`MAC_System_Time_Seconds_Update` `0x3344` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TSS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSS` `RW 0x0`
`MAC_System_Time_Nanoseconds_Update` `0x3348` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ADDSUB` `RW 0x0`	`TSSS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSSS` `RW 0x0`
`MAC_Timestamp_Addend` `0x3352` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TSAR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSAR` `RW 0x0`
`MAC_System_Time_Higher_Word_Seconds` `0x3356` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSHWR` `RW 0x0`
`MAC_Timestamp_Status` `0x3360` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_30` `RO 0x0`		`ATSNS` `RO 0x0`					`ATSSTM` `RO 0x0`	`Reserved_23_20` `RO 0x0`				`ATSSTN` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXTSC` `RO 0x0`	`TTSNS` `RO 0x0`					`TSTRGTERR3` `RO 0x0`	`TSTARGT3` `RO 0x0`	`TSTRGTERR2` `RO 0x0`	`TSTARGT2` `RO 0x0`	`TSTRGTERR1` `RO 0x0`	`TSTARGT1` `RO 0x0`	`TSTRGTERR0` `RO 0x0`	`AUXTSTRIG` `RO 0x0`	`TSTARGT0` `RO 0x0`	`TSSOVF` `RO 0x0`
`MAC_Tx_Timestamp_Status_Nanoseconds` `0x3376` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXTSSMIS` `RO 0x0`	`TXTSSLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXTSSLO` `RO 0x0`
`MAC_Tx_Timestamp_Status_Seconds` `0x3380` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TXTSSTSHI` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TXTSSTSHI` `RO 0x0`
`MAC_Tx_Timestamp_Status_PktID` `0x3384` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_10` `RO 0x0`						`PKTID` `RO 0x0`
`MAC_Auxiliary_Control` `0x3392` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_31_8` `RO 0x0`								`Reserved_ATSEN3` `RO 0x0`	`Reserved_ATSEN2` `RO 0x0`	`ATSEN1` `RW 0x0`	`ATSEN0` `RW 0x0`	`Reserved_3_1` `RO 0x0`			`ATSFC` `RW 0x0`
`MAC_Auxiliary_Timestamp_Nanoseconds` `0x3400` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31` `RO 0x0`	`AUXTSLO` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AUXTSLO` `RO 0x0`
`MAC_Auxiliary_Timestamp_Seconds` `0x3404` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`AUXTSHI` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`AUXTSHI` `RO 0x0`
`MAC_Timestamp_Ingress_Asym_Corr` `0x3408` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OSTIAC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`OSTIAC` `RW 0x0`
`MAC_Timestamp_Egress_Asym_Corr` `0x3412` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`OSTEAC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`OSTEAC` `RW 0x0`
`MAC_Timestamp_Ingress_Corr_Nanosecond` `0x3416` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TSIC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSIC` `RW 0x0`
`MAC_Timestamp_Ingress_Corr_Subnanosecond` `0x3420` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSICSNS` `RW 0x0`								`Reserved_7_0` `RO 0x0`
`MAC_Timestamp_Egress_Corr_Nanosecond` `0x3424` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TSEC` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSEC` `RW 0x0`
`MAC_Timestamp_Egress_Corr_Subnanosecond` `0x3428` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSECSNS` `RW 0x0`								`Reserved_7_0` `RO 0x0`
`MAC_PPS_Control` `0x3440` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31` `RO 0x0`	`Reserved_TRGTMODSEL3` `RO 0x0`		`Reserved_28_27` `RO 0x0`		`Reserved_PPSCMD3` `RO 0x0`			`Reserved_23` `RO 0x0`	`Reserved_TRGTMODSEL2` `RO 0x0`		`Reserved_20_19` `RO 0x0`		`Reserved_PPSCMD2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_15` `RO 0x0`	`TRGTMODSEL1` `RW 0x0`		`Reserved_12_11` `RO 0x0`		`PPSCMD1` `RW 0x0`			`Reserved_7` `RO 0x0`	`TRGTMODSEL0` `RW 0x0`		`PPSEN0` `RW 0x0`	`PPSCTRL0_PPSCMD0` `RW 0x0`
`MAC_PPS0_Target_Time_Seconds` `0x3456` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TSTRH0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSTRH0` `RW 0x0`
`MAC_PPS0_Target_Time_Nanoseconds` `0x3460` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TRGTBUSY0` `RW 0x0`	`TTSL0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TTSL0` `RW 0x0`
`MAC_PPS0_Interval` `0x3464` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PPSINT0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PPSINT0` `RW 0x0`
`MAC_PPS0_Width` `0x3468` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PPSWIDTH0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PPSWIDTH0` `RW 0x0`
`MAC_PPS1_Target_Time_Seconds` `0x3472` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TSTRH1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TSTRH1` `RW 0x0`
`MAC_PPS1_Target_Time_Nanoseconds` `0x3476` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TRGTBUSY1` `RW 0x0`	`TTSL1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TTSL1` `RW 0x0`
`MAC_PPS1_Interval` `0x3480` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PPSINT1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PPSINT1` `RW 0x0`
`MAC_PPS1_Width` `0x3484` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PPSWIDTH1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PPSWIDTH1` `RW 0x0`
`MAC_PTO_Control` `0x3520` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DN` `RW 0x0`								`PDRDIS` `RW 0x0`	`DRRDIS` `RW 0x0`	`APDREQTRIG` `RW 0x0`	`ASYNCTRIG` `RW 0x0`	`Reserved_3` `RO 0x0`	`APDREQEN` `RW 0x0`	`ASYNCEN` `RW 0x0`	`PTOEN` `RW 0x0`
`MAC_Source_Port_Identity0` `0x3524` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SPI0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SPI0` `RW 0x0`
`MAC_Source_Port_Identity1` `0x3528` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SPI1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SPI1` `RW 0x0`
`MAC_Source_Port_Identity2` `0x3532` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SPI2` `RW 0x0`
`MAC_Log_Message_Interval` `0x3536` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`LMPDRI` `RW 0x0`								`Reserved_23_11` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_23_11` `RO 0x0`					`DRSYNCR` `RW 0x0`			`LSI` `RW 0x0`