MAC_Tx_Configuration

Speed Selection.
  
  Software programs these bits to instruct the MAC to operate in one of the following possible speeds:
   - 3'b000     Reserved     
   - 3'b001     Reserved
   - 3'b010     2.5G    GMII
   - 3'b011     1G      GMII
   - 3'b100     100M    MII
   - 3'b101     Reserved
   - 3'b110     Reserved
   - 3'b111     10M     MII
  These bits must be programmed only once; after a hardware reset and before the transmitter and receiver are enabled (by bit 0 of this register and bit 0 of the MAC_Rx_Configuration register).

Reserved.

Reserved.

Reserved.

Reserved.

Reserved.

Reserved.

Source Address Insertion or Replacement Control.
  
  This field controls the source address insertion or replacement for all transmitted packets. Bit 22 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits[21:20]:
  
  2'b0x: The SA insertion-replacement is controlled by one of the following:
   - mti_sa_ctrl_i input signal in XGMAC-CORE configuration
   - SAIC field (Bits[26:24]) of Transmit Control Word in XGMAC-MTL configuration
   - SAIC field (Bits[25:23]) of TDES3 Normal Descriptor in XGMAC-AXI configuration
  2'b10: 
   - If Bit 22 is set to 0, the MAC inserts the content of the MAC Address 0 registers (MAC_Address0_High and MAC_Address0_Low) in the SA field of all transmitted packets.
   - If Bit 22 is set to 1 and the Enable MAC Address Register 1 option is selected while configuring the controller, the MAC inserts the content of the MAC Address 1 registers (MAC_Address1_High and MAC_Address1_Low) in the SA field of all transmitted packets.
  2'b11: 
   - If Bit 22 is set to 0, the MAC replaces the content of the MAC Address 0 registers (MAC_Address0_High and MAC_Address0_Low) in the SA field of all transmitted packets.
   - If Bit 22 is set to 1 and the MAC Address Register 1 is enabled, the MAC replaces the content of the MAC Address 1 registers (MAC_Address1_High and MAC_Address1_Low) in the SA field of all transmitted packets.
  Note:
   - Changes to this field take effect only on the start of a packet. If you write to this register field when a packet is being transmitted, only the subsequent packet can use the updated value, that is, the current packet does not use the updated value.

Reserved.

Reserved.

Reserved.

Jabber Disable.
  
  When this bit is set, the DWC_xgmac disables the jabber timer on the transmitter. Transmission of up to 16383-byte packets is supported.
  
  When this bit is reset, DWC_xgmac cuts off the transmitter if the application sends more than 2048 bytes of data (10240 bytes if JE (in MAC_Rx_Configuration register is set high) during transmission.

Reserved.

Link Up or Down.
  
  This bit indicates whether the link is up or down during transmission of configuration in the RGMII interface.
   - 1'b0: Link down
   - 1'b1: Link up

Transmit Configuration in RGMII.
  
  When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, port. When this bit is reset, no such information is driven to the PHY. The details of this feature are provided in the following sections:
   - 1'b0: Disable Transmit Configuration in RGMII
   - 1'b1: Enable Transmit Configuration in RGMII

IPG Control

  When this bit is set, the minimum IPG is increased in steps of 32 bits from the default 96 bits, depending on the programming of the IPG field.
  
  When this bit is reset, the minimum IFG is decreased in steps of 8 bits from the default 96 bits, depending on the programming of the IPG field.

Inter-Packet Gap
  
  These bits control the minimum IPG between packets during transmission. When IFP is cleared, the minimum IPG between transmitted packets is reduced in GMII mode. The corresponding IPG values are given as follows.
   - 3'b000: 96 bit times
   - 3'b001: 88 bit times
   - 3'b010: 80 bit times
   - 3'b011: 72 bit times
   - 3'b100: 64 bit times
   - 3'b101: 3'b111: Reserved
  In the half-duplex mode, the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower values are not considered. 
  
  When a JAM pattern is transmitted because of backpressure activation, the MAC does not consider the minimum IPG. 
 
  When IFP is set, the minimum IPG is increased in steps of 32 bits as follows.
  
  The EIPG bits (in MAC_Extended_Configuration register) along with IPG bits gives a 10-bit value to control the required IPG as follows: 
   - {EIPG,IPG}: Minimum Inter-Packet Gap
   - 10'h000: 96 bit times
   - 10'h001: 128 bit times
   - 10'h002: 160 bit times
   - 10'h003: 192 bit times
   - 10'h004: 224 bit times
   - ...
   - 10'h3FF: 32832 bit times

IFG Stretch Ratio.
  
  This value controls the number of bytes in a transmitted packet for which one octet of IDLE is added to the IFG. To operate DWC_xgmac for 10GBASE-W (WIS layer), the value must be 13 (decimal).
  
  Note that 0 is not a valid value and must not be written. Before enabling ISM (IFG Stretch Mode) bit, this ISR number must be programmed to a non-zero value.

IFG Stretch Mode.
  
  When this bit is set, DWC_xgmac enforces extended inter-packet spacing (one extra octet of IDLE for every ISR (IFG Stretch Ratio) number of bytes) to support less-than-10-Gbps data rates.
  
  When this bit is reset, inter-packet gap extension is not performed.

Reserved.

Disable DIC Algorithm.
  
  When this bit is set, the Deficit Idle Count (DIC) algorithm is disabled and DWC_xgmac always has a minimum IFG of 12 bytes between transmitted packets.
  
  When reset to zero, the DIC is activated and the minimum IFG varies between 9 and 15 bytes.

Transmitter Enable.

  When this bit is set, the Tx state machine of the MAC is enabled for transmission on the GMII interface. 
  
  When this bit is reset, the MAC Tx state machine is disabled after it completes the transmission of the current packet. The Tx state machine does not transmit any more packets.