Intel® FPGAs and Programmable Devices / Documentation / White Papers

White Papers

Title PDF Published Date End market Device
40-nm FPGAs and the Defense Electronic Design Organization.pdf -
40-nm FPGAs: Architecture and Performance Comparison.pdf -
A New FPGA Architecture and Leading-Edge FinFET Process Technology Promise to Meet Next-Generation System Requirements.pdf -
A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services.pdf -
A Significant Technology Advancement in High-Speed Link Modeling and Simulation.pdf -
A Tailored Approach to FPGA Process Selection.pdf -
Abstract – Floating Point.pdf -
Accelerating DSP Designs with the Total 28-nm DSP Portfolio.pdf -
Accelerating Genomics Research with OpenCL™ and FPGAs.pdf -
Accelerating Memory Bound AI Inference Workloads with Intel® Stratix® 10 MX Devices.pdf -
Accelerating WiMAX System Design with FPGAs.pdf -
Achieving Lowest System Cost with Midrange 28-nm FPGAs.pdf -
Achieving Lowest System Power with Low-Power 28-nm FPGAs.pdf -
Achieving the Highest Levels of Integration in Programmable Logic.pdf -
Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs.pdf -
Addressing 5G Network Function Requirements.pdf -
Addressing Next-Generation Memory Requirements Using Intel® FPGAs and HMC Technology.pdf -
Addressing SWaP Challenges in Military Platforms With 65-nm FPGAs and Structured ASICs.pdf -
Advanced System Management with Analog Non-Volatile FPGAs.pdf -
Altera FPGAs Drive Sharp Two-Way Viewing Angle LCD Architecture.pdf -
Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 White Paper.pdf -
Altera at 40 nm: Jitter, Signal Integrity, Power, and Process Optimized.pdf -
Altera’s 28-nm FPGAs Optimized for Broadcast Video Applications.pdf -
An Alternative to Bus-Based Interconnects for Large-Scale Design.pdf -
An Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II and Virtex-II Pro Devices.pdf -
An Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II and Virtex-II Pro Devices.pdf -
An Independent Analysis of Altera’s FPGA Floating-point DSP Design Flow.pdf -
An Independent Analysis of Floating-point DSP Design Flow and Performance on Altera 28-nm FPGAs.pdf -
Anti-Tamper Capabilities in FPGA Designs.pdf -
Applying Graphics to FPGA-Based Solutions.pdf -
Architecture and Component Selection for Optimized SDR Applications.pdf -
Architecture and Component Selection for Optimized SDR Applications.pdf -
Are FPGAs the answer to the “Compute Gap?”.pdf 2018-12-21
Arria V FPGA White Papers.pdf -
Artificial Intelligence and Machine Learning.pdf -
Assessing FPGA DSP Benchmarks at 40 nm.pdf -
Automating DSP Simulation and Implementation of Military Sensor Systems.pdf -
Avoiding PCB Design Mistakes in FPGA-Based Systems.pdf -
Backplane Applications with 28 nm FPGAs White Paper.pdf -
Bare-Metal, RTOS, or Linux? Optimize Real-Time Performance with Altera SoCs.pdf -
Benefits of Altera’s High-Speed DDR2 SDRAM Memory Interface Solution.pdf -
Board Design Guidelines for LVDS Systems.pdf -
Boost Performance of Video Analytics with the Intel® Vision Accelerator Design with Intel® Arria® 10 FPGA.pdf -
Boosting System Performance with External Memory Solutions.pdf -
Building Flexible, Cost-Efficient Broadband Access Equipment Line Cards.pdf -
Building Flexible, Cost-Efficient Broadband Access Line Cards.pdf -
Building a PoC of Segment Routing at 100G Using FPGA Smart NIC and P4 Language.pdf -
Compromises of Using a 10-Gbps Transceiver at Other Data Rates.pdf -
Crest Factor Reduction for OFDM-Based Wireless Systems.pdf -
Customizing Multi-Service Access Network Silicon.pdf -
DO-254 Support for FPGA Design Flows.pdf -
DPA Circuitry and rx_dpa_locked Signal Behavior in Stratix III Devices.pdf -
DSP-FPGA System Partitioning for MIMO-OFDMA Wireless Basestations.pdf -
Delivering Intelligent Bandwidth with Intel® Stratix® 10 Transceiver Tiles.pdf -
Delivering the Right Power and Performance for 28 nm High-End FPGAs White Paper.pdf -
Delivering the Right Power and Performance for 28 nm High-End FPGAs White Paper.pdf -
Design Security in Stratix III Devices.pdf -
Designing Filters for High Performance.pdf -
Designing High-Performance DSP Hardware Using Catapult C Synthesis and Altera Accelerated Libraries.pdf -
Designing With Confidence for Military SDR Production Applications.pdf -
Designing and Using FPGAs for Double-Precision Floating Point Math.pdf -
Electronic Warfare Design With PLDs and High-Speed Transceivers.pdf -
Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs.pdf -
Enabling High-Performance DSP Applications with Arria V or Cyclone V Variable-Precision DSP Blocks.pdf -
Enabling High-Performance DSP Applications with Stratix V Variable-Precision DSP Blocks.pdf -
Enabling High-Performance Floating-Point Designs.pdf -
Enabling Impactful DSP Designs on FPGAs with Hardened Floating-Point Implementation.pdf -
Enabling Quality of Service With Customizable Traffic Managers.pdf -
Enhancing High-Speed Telecommunications Networks with FEC.pdf -
Enhancing Robust SEU Mitigation with 28-nm FPGAs.pdf -
Error Correction Code in SoC FPGA-Based Memory Systems.pdf -
Expand Server Memory Capacity and Improve Server Performance with Intel® Stratix® 10 FPGAs and Intel Optane™ DC Persistent Memory.pdf -
Expect a Breakthrough Advantage in Next-Generation FPGAs White Paper.pdf -
Expect a Breakthrough Advantage in Next-Generation FPGAs White Paper.pdf -
Exploiting Unstructured Sparsity on Next-Generation Datacenter Hardware.pdf -
Extending Silicon Convergence with Technology Innovations at 20 nm.pdf -
Extending Transceiver Leadership at 28 nm.pdf -
FPGA Architecture White Paper.pdf -
FPGA Coprocessing Evolution: Sustained Performance Approaches Peak Performance.pdf -
FPGA Design Security Solution Using MAX II Devices.pdf -
FPGA vs. DSP Design Reliability and Maintenance.pdf -
FPGAs Power High-Performance Computing.pdf -
FPGAs at 40 nm and >10 Gbps: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers.pdf -
Finding Acceleration in a Video-Centric World.pdf -
Finding an Efficient Virtual Network Functon Architecture for Next-Generation Telecommunications Infrastructure.pdf -
First Demonstration of Chip-to-Module Electrical Channel Interoperability over OIF CEI-28G-VSR Compliant Links.pdf -
Floating-Point Compiler: Increasing Performance With Fewer Resources.pdf -
Fulfilling Technology Needs for 40G–100G Network-Centric Operations and Warfare.pdf -
Gain Flexibility, Lower Costs in Display Control Through Integration With FPGAs.pdf -
Guidance for Accurately Benchmarking FPGAs.pdf -
Hardware in the Loop from the MATLAB/Simulink Environment.pdf -
Hardware/Software Co-Verification Using FPGA Platforms.pdf -
High-Definition Video Deinterlacing Using FPGAs.pdf -
How to Upgrade a DDR SDRAM Controller MegaCore Function v2.1 Design to v2.2 White Paper.pdf -
Implementation of the Smith-Waterman Algorithm on a Reconfigurable Supercomputing Platform.pdf -
Implementing Digital IF & Digital Predistortion Linearizer Functions with Programmable Logic.pdf -
Implementing FIR Filters and FFTs with 28-nm Variable-Precision DSP Architecture.pdf -
Implementing LED Drivers In MAX Devices.pdf -
Implementing Next-Generation Passive Optical Network Designs with FPGAs.pdf -
Implementing a Flexible CPLD-Only Digital Dashboard for Automobiles.pdf -
Implementing a Queue Manager in Traffic Management Systems White Paper.pdf -
Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs.pdf -
Improving Pin-to-Pin Timing in Stratix & Stratix GX Devices.pdf -
Increase Performance in Imaging Applications by Integrating DSP Functions With FPGAs.pdf -
Increase Performance in Video and Image Processing Applications With FPGA Integration.pdf -
Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs.pdf -
Increasing Efficiency with Hard Memory Controllers in Low-Cost 28 nm FPGAs White Paper.pdf -
Integrating 100-GbE Switching Solutions on 28-nm FPGAs.pdf -
Intel Arria 10 Performance Benchmarking Methodology and Results.pdf -
Intel® Agilex™ FPGAs Deliver a Game-Changing Combination of Flexibility and Agility for the Data-Centric World.pdf - Intel® Agilex™
Intel® FPGAs Accelerate Intel® Xeon® Scalable Processors in Servers and High-End Embedded Systems.pdf - Intel® Stratix® 10 DX
Intel® Stratix® 10 MX Devices with Samsung* HBM2 Solve the Memory Bandwidth Challenge.pdf -
Introducing Innovations at 28 nm to Move Beyond Moore’s Law.pdf -
JESD204A for Wireless Base Station and Radar Systems.pdf -
Leveraging the Intel® HyperFlex™ FPGA Architecture in Intel Stratix® 10 Devices to Achieve Maximum Power Reduction.pdf -
Logic Efficiency in Stratix, Virtex-II & Virtex-II Pro Devices.pdf -
Low Latency GRE Processing Accelerator Evaluation.pdf -
Low-Cost Integration of Serial EEPROMs and Flash Memory Devices.pdf -
Lower Costs in Broadcasting Applications With Integration Using FPGAs.pdf -
MAX II I/O Characteristics During Hot Socketing.pdf -
MAX II Logic Element to Macrocell Conversion Methodology White Paper.pdf -
Meeting the Performance and Power Imperative of the Zettabyte Era with Generation 10 White Paper.pdf -
Microsoft Word - Accelerating_Nios_II_Ethernet_Applications_wp.doc.pdf -
Microsoft Word - signal-integrity_s2-v4.doc.pdf -
Microsoft Word - sonet_backplane.doc.pdf -
Microsoft Word - wp_s2v4perf_rev.doc.pdf -
Microsoft Word - wpstxiiple_rev.doc.pdf -
Military Benefits of the Managed Risk Process at 40 nm.pdf -
Military Productivity Factors in Large FPGA Designs.pdf -
Minimizing Ground Bounce & VCC Sag.pdf -
OPC UA TSNA new Solution for Industrial Communication.pdf 2019-11-13
OTN Transport of Baseband Radio Serial Protocols in C-RAN Architecture for Mobile Network Applications.pdf -
OpenCL on FPGAs for GPU Programmers.pdf -
Optimizing Radar and Advanced Sensor Functions With FPGAs.pdf -
Overcome Copper Limits with Optical Interfaces.pdf -
Overcome Design Challenges with an Innovative IP Scalability, Integration, and Delivery Model.pdf -
Overcome High-Speed I/O Verification Challenges with Stratix V On-Die Instrumentation.pdf -
PDN Design and FPGA Transceiver Performance.pdf -
PLC Architecture in the Industry 4.0 World: Challenges, Trends, and Solutions.pdf -
POS-PHY Level 4 MegaCore Function Errata Sheet.pdf -
POS-PHY Level 4 MegaCore Function Errata Sheet.pdf -
Power-Optimized Solutions for Telecom Applications.pdf -
Providing Battery-Free, FPGA-Based RAID Cache Solutions.pdf -
Reap Rewards by Minimizing Risk: Altera’s Strategies for Delivering the Benefits of the 65-nm Process Node.pdf -
Reduce Manufacturing Costs by Integrating Flash Device Programming.pdf -
Reduce System Costs by Integrating PCI Interface Functions Into CPLDs.pdf -
Reduce Total System Cost in Portable Applications Using Zero-Power CPLDs.pdf -
Reduce Total System Cost in Portable Applications Using Zero-Power CPLDs.pdf -
Reducing Power Consumption and Increasing Bandwidth on 28-nm FPGAs.pdf -
Reducing Total System Cost with Low-Power 28 nm FPGAs.pdf -
Reducing the Cost of Wireless Backhauling Through Circuit Emulation.pdf -
Robust SEU Mitigation With Stratix III FPGAs.pdf -
SEmulation: Turbocharging the FPGA Development Process.pdf -
Satisfying the Demand for Rapid Feature Enhancement in Consumer Display Products.pdf -
Secure Computing Environment for SoCs and FPGAs.pdf -
Selecting the Correct High Speed Transceiver Solution.pdf -
Selecting the Ideal FPGA Vendor for Military Programs.pdf -
SerialLite Protocol Overview White Paper.pdf -
Shifting from Software to Hardware for Network Security.pdf -
Six Ways to Replace a Microprocessor With a CPLD.pdf -
Six Ways to Replace a Microprocessor With a CPLD.pdf -
Strategic Considerations for Emerging SoC FPGAs.pdf -
Stratix GX & Switch Fabric Systems White Paper.pdf -
Stratix GX in Storage Applications White Paper.pdf -
Stratix II DDR2 System Validation Summary.pdf -
Stratix II DSP Performance.pdf -
Stratix II vs. Virtex-4 Density Comparison White Pap.pdf -
Stratix II vs. Virtex-4 Power Comparison & Estimation Accuracy White Paper.pdf -
Stratix III FPGAs vs. Xilinx Virtex-5 Devices: Architecture and Performance Comparison.pdf -
Stratix vs. Virtex-II Pro FPGA Performance Analysis.pdf -
Supercharging Design Performance and Productivity with Altera FPGAs and Best-in-Class IP.pdf -
Superior CPRI over OTN Front-haul Solutions.pdf -
Supporting Enterprise-Grade Flash with Programmable State Machines.pdf -
Synchronizing Mechatronic Systems in Real-Time Using FPGAs and Industrial Ethernet Communications.pdf -
Synchronous Ethernet Solutions with Altera FPGAs and Silicon Labs Jitter-Attenuating PLLs White Paper.pdf -
System Design with Advance FPGA Timing Models.pdf -
Taking Advantage of Advances in FPGA Floating-Point IP Cores.pdf -
The Altera DDR & DDR2 SDRAM Controller Compiler Frequently Asked Questions (FAQ) white paper.pdf -
The Breakthrough Advantage for FPGAs with Tri-Gate Technology White Paper.pdf -
The Emerging Need for Fronthaul Compression.pdf -
The Evolution of High-Speed Transceiver Technology.pdf -
The Expanding Role of FPGAs in DSP Applications White Paper.pdf -
The JBlaster Software Driver: An Embedded Solution to the JTAG Configuration.pdf -
The efficiency of the Altera DDR & DDR2 SDRAM Controller Compiler white paper.pdf -
TimeQuest Timing Analyzer: Native SDC Support for Timing Analysis of FPGA-Based Designs.pdf -
Traffic Management in Stratix GX Devices White Paper.pdf -
Transferring High-Speed Data over Long Distances with Combined FPGA and Multichannel Optical Modules.pdf -
Transient Voltage Protection for Stratix GX Devices.pdf -
Turning Video Analytics into Business Value.pdf -
Understanding How the New HyperFlex™ Architecture Enables Next-Generation High-Performance Systems.pdf -
Understanding Peak Floating-Point Performance Claims.pdf -
Understanding and Meeting FPGA Power Requirements White Paper.pdf -
User-Customizable ARM-Based SoCs for Next-Generation Embedded Systems.pdf -
Using 10-Gbps Transceivers in 40G/100G Applications.pdf -
Using LEDs as Light-Level Sensors and Emitters.pdf -
Using Parity to Detect Errors White Paper.pdf -
Using Stratix GX in HDTV Video Production Applications.pdf -
Using Zero-Power CPLDs to Substantially Lower Power Consumption in Portable Applications.pdf -
Using Zero-Power CPLDs to Substantially Lower Power Consumption in Portable Applications.pdf -
Using the Intel Flash Memory-Based EPC4, EPC8 & EPC16 Devices.pdf -
Using the Quartus II Software to Maximize Performance in the HyperFlex Architecture.pdf -
Utilizing Leveling FPGAs in DDR3 SDRAM Memories.pdf -
Video Streaming with Near-Zero Latency Using Altera Arria V FPGAs and Video and Image Processing Suite Plus the Right Encoder.pdf -
Zynq to SoC FPGA Design Migration Tips and Techniques.pdf -
soc_design.book.pdf -