Yield analysis engineers have always performed end-of-line yield analysis at Intel’s silicon wafer factories (fabs). One thing engineers look for are gross failure areas (GFAs)--patterns that indicate a problem has occurred in the fab. Different problems cause different-looking patterns. Examples of problems include a tool beginning to fail, the fleet of tools running mismatched or a change in one processing step inadvertently impacting another step.
As the number of products and volume grow in Intel’s manufacturing environment, a manual detection approach to yield analysis poses several challenges:
Limited human-hour resources prevent engineers from reviewing and documenting every issue in every wafer in every lot.
Detection accuracy depends on an engineer’s experience level.
Knowledge sharing between fabrication sites is cumbersome and slow.
Intel IT is changing the paradigm of yield analysis from this manual, reactive “pull” approach to a proactive “push” approach. The more quickly fab issues are identified, the sooner they get fixed and overall yield is improved.
The solution encompasses three key elements:
AI model. We developed a dedicated AI workflow that uses machine-learning, deep-learning and image-processing techniques to perform automated pattern recognition. AI can identify and document multiple GFAs per wafer, and learn to capture patterns that affect yield.
Autonomous end-to-end detection. The legacy GFA tools were limited and required manual intervention and manual queries. Now, the automated push approach produces data for root cause analysis and calculates yield impact trends.
Holistic integration. The algorithms’ results are seamlessly integrated into the existing manufacturing workflow methods and tools, which improves ease of use and our ability to extend the algorithms’ business value to additional use cases.
The combined solution—algorithm, automation and integration—currently provides two services:
Baseline pattern detection. For 100 percent of end-of-line wafers, the solution can use the pattern examples provided to it to automatically determine if a wafer has a known (baseline) inline issue, without manual intervention. This aspect of the solution looks for issues we know exist in the manufacturing environment to some extent. The solution provides >90 percent accuracy in detecting baseline patterns.
Unknown pattern detection. The solution can also report information about all the patterns that are currently impacting yield and the level of impact. Yield analysis engineers can use the report to identify new insights, such as a new pattern, a known pattern that has a changed definition or a change in level of yield impact. This latter information can help engineers set their investigation priorities. Once the engineers complete the root cause analysis for a previously unknown pattern, the new pattern is added to the baseline pattern repository, and the AI model is retrained to recognize it.
Our unique solution enables end-of-line issue detection to identify multiple issues on the same wafer, and to examine 100 percent of wafers in every lot. The combination of artificial intelligence (AI) and yield analysis engineers’ knowledge enables them to support more products, use knowledge captured collectively across fabs and shorten time to resolution.