Developer Events

June 29

Take a tour of a new data-science workstation solution that's purpose-built to shrink the time data practitioners spend on model development and optimization.

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Wednesday, June 29, 9:00 a.m.-10:00 a.m. (PDT)

This class teaches the techniques used by FPGA design specialists to close timing on designs that surpass the normal limits of performance. You will use a remote computer connected through Webex* for labs. No set up is needed.

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June 29-30, 9:00 a.m.-1:30 p.m. (PDT)

June 30

Get hands-on experience using the Intel® AI Analytics Toolkit to explore predictive modeling techniques based on decision trees. Take popular decision-tree algorithms (used for regression and classification tasks) and address the challenge of handling training when data sizes increase.

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June 30, 9:00 a.m.-11:00 a.m. (PDT)

July 6

Learn how to quickly build designs for Intel® FPGA devices using the Platform Designer system-level integration tool (part of the Intel® Quartus® Prime Software). You will use a remote computer connected through Webex* for labs. No set up is needed.

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July 6, 2022

9:00 a.m.-1:30 p.m. (PDT)

Learn how to use the Intel® Quartus® Prime Pro Edition Software. Correlate these steps to the general flow of an FPGA design process. You will use a remote computer connected through Webex* for labs. No set up is needed.

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July 6-7, 2022

9:00 a.m.-1:30 p.m. (PDT)

July 7

Learn the basics of this tool: The standard interfaces it supports, how to create new or add to existing HDL designs to implement these interfaces, and how to integrate custom components into the tool. You will use a remote computer connected through Webex* for labs. No set up is needed.

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July 7, 2022

9:00 a.m.-1:30 p.m. (PDT)

July 11

Get a general introduction to the Verilog language and its use in programmable logic design. The class covers the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.

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July 11-13, 2022

10:00 a.m.-2:30 p.m. (CET)

July 12

Join us for this live (and free) virtual event focused on the latest AI technology advancements that can start or advance your development career.

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July 12, 2022

9:00 a.m. - 5:00 p.m. Pacific daylight time (PDT)

July 13

Learn how to perform reduction operations in oneAPI using SYCL or oneDPL, and learn the advantages of each approach.

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July 13, 2022

9:00 a.m. Pacific daylight time (PDT)

Get a general introduction to the Verilog language and its use in programmable logic design. The class covers the basic constructs used in the simulation and synthesis environments. You will use a remote computer connected through Webex* for labs. No set up is needed.

Register

July 13-14, 2022

9:00 a.m.-1:30 p.m. (PDT)

July 26

As FPGA designs become more complex, a larger part of development time is spent verifying designs. You will use a remote computer connected through Webex* for labs. No set up is needed. 

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July 26, 2022

9:00 a.m.-1:30 p.m. (PDT)

July 27

Learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and CPLDs. You will use a remote computer connected through Webex* for labs. No set up is needed. 

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July 27-28, 2022

9:00 a.m.-1:30 p.m. (PDT)