Hard Processor System Component Reference Manual: Agilex™ 3 SoCs

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ID 851703
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Agilex™ 3 Hard Processor System Component 2. Configuring the Agilex™ 3 Hard Processor System Component 3. Simulating the Agilex™ 3 HPS Component 4. Simulating the Agilex™ 3 HPS bridges (H2F, LWH2F, and F2SDRAM) 5. Design Guidelines 6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 3 SoCs
1. Introduction to the Agilex™ 3 Hard Processor System Component x
1.1. Release Notes 1.2. Micro Processor Unit 1.3. Application Processor Subsystem 1.4. Peripheral Subsystem 1.5. CoreSight* Debug Components 1.6. Interconnect 1.7. FPGA Bridges 1.8. Introduction to the Agilex™ 3 Hard Processor System Component Revision History
1.1. Release Notes x
1.1.1. HPS IP 7.0.0
2. Configuring the Agilex™ 3 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. HPS-FPGA Interfaces 2.3. SDRAM 2.4. HPS Clocks, Reset, Power 2.5. I/O Delays 2.6. Pin Mux and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the Agilex™ 3 Hard Processor System Component Revision History
2.2. HPS-FPGA Interfaces x
2.2.1. General 2.2.2. HPS FPGA Bridges 2.2.3. DMA Controller Interface 2.2.4. Interrupts
2.2.1. General x
2.2.1.1. Enable MPU Standby and Event Signals 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB* Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable SWJ-DP JTAG Interface 2.2.1.6. Enable FPGA Cross Trigger Interface 2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.2.2. HPS FPGA Bridges x
2.2.2.1. FPGA to HPS Subordinate 2.2.2.2. FPGA to SDRAM Subordinate 2.2.2.3. HPS to FPGA Manager 2.2.2.4. Lightweight HPS to FPGA Manager
2.2.4. Interrupts x
2.2.4.1. FPGA-to-HPS 2.2.4.2. HPS-to-FPGA
2.3. SDRAM x
2.3.1. Configurations for HPS IP 2.3.2. Configurations for HPS EMIF IP 2.3.3. Graphical Connections of HPS to HPS-EMIF 2.3.4. Configuration when using ECC 2.3.5. Configuration of HPS EMIF Calibration Settings 2.3.6. Supported Memory Protocols Among Device Families 2.3.7. IO96 Bank and Lane Usage for HPS EMIF 2.3.8. Quartus Report of I/O Bank Usage 2.3.9. Debugging with the External Memory Interface Debug Toolkit
2.4. HPS Clocks, Reset, Power x
2.4.1. Input Clocks 2.4.2. PLL Clocks 2.4.3. Power and Resets
2.4.1. Input Clocks x
2.4.1.1. External Clocks 2.4.1.2. FPGA-to-HPS Clocks 2.4.1.3. Peripheral FPGA Clocks
2.4.2. PLL Clocks x
2.4.2.1. Main PLL Output 2.4.2.2. Peripheral PLL Output 2.4.2.3. MPU Clocks 2.4.2.4. NOC Clocks 2.4.2.5. Peripheral Clocks 2.4.2.6. HPS-to-FPGA User Clocks
2.4.3. Power and Resets x
2.4.3.1. Power Configurations 2.4.3.2. Reset Signals
2.6. Pin Mux and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. EMAC PTP Interface 2.6.3. HPS I/O Open Drain 2.6.4. HPS I/O Locations
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
2.6.1.1. Auto-Place IP x
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC x
2.6.1.1.1.1. HPS IO Placement Priority
2.6.1.2. Advanced x
2.6.1.2.1. Advanced IP Placement 2.6.1.2.2. Advanced FPGA Placement
3. Simulating the Agilex™ 3 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interface 3.3. FPGA-to-HPS AXI* Subordinate Interface 3.4. FPGA-to-SDRAM AXI* Subordinate Interface 3.5. HPS-to-FPGA AXI* Manager Interface 3.6. Lightweight HPS-to-FPGA AXI* Manager Interface 3.7. Simulating the Agilex™ 3 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. RTL Simulation Setup Scripts
3.1.3. RTL Simulation Setup Scripts x
3.1.3.1. QuestaSim* Simulation Steps 3.1.3.2. Cadence® Xcelium* Simulation Steps 3.1.3.3. Synopsys* VCS* MX Simulation Steps 3.1.3.4. Riviera-PRO* Simulation Steps 3.1.3.5. Synopsys* VCS* Simulation Steps 3.1.3.6. VSIM Command Line Aliases and Variables
3.2. Clock and Reset Interface x
3.2.1. Clock Interface 3.2.2. Reset Interface
4. Simulating the Agilex™ 3 HPS bridges (H2F, LWH2F, and F2SDRAM) x
4.1. Setting up the HPS Component for Simulation 4.2. Generating the HPS Simulation Model in Platform Designer 4.3. Editing the TestBench scripts 4.4. Running the TestBench scripts 4.5. Simulating the Agilex™ 3 HPS Bridges (H2F, LWH2F, and F2SRAM) Revision History
4.3. Editing the TestBench scripts x
4.3.1. my_simple_tb.sv 4.3.2. test_lwh2f.sv 4.3.3. test_h2f_128b.sv 4.3.4. test_f2sdram_256b.sv
4.4. Running the TestBench scripts x
4.4.1. Questa* Intel® FPGA Edition Simulation Steps
5. Design Guidelines x
5.1. HPS System Reset Considerations 5.2. Design Guidelines Revision History
1. Introduction to the Agilex™ 3 Hard Processor System Component
2. Configuring the Agilex™ 3 Hard Processor System Component
3. Simulating the Agilex™ 3 HPS Component
4. Simulating the Agilex™ 3 HPS bridges (H2F, LWH2F, and F2SDRAM)
5. Design Guidelines
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 3 SoCs

2.4.2.4. NOC Clocks

This section contains options for setting the PSS NOC clocks and the associated peripherals.

Table 13.  PSS NOC Clocks and Peripherals Description
Parameter Name Parameter Value Parameter Description

NOC Clock Source Select

MainC3, PeriphC1

Select the source for the NOC clock

L4 Free Clock Divider

Div2, Div4

Divider setting for l4_sys_free_clk

L4 Peripheral Clock Divider

Div1, Div2

Divider setting for l4_mp_clk

L4 Slow Peripheral Clock Divider

Div2, Div4

Divider setting for l4_sp_clk

Soft PHY Clock Divider

Div1, Div2, Div4

Divider setting for phy_clock

CoreSight Clock Divider

Div1, Div2, Div4, Div8

Divider setting for cs_at_clk

CoreSight Debug APB Clock Divider

Div1, Div4

Divider setting for cs_pdbg_clk

CoreSight Trace IO Clock Divider

Div1, Div2, Div4, Div8

Divider setting for cs_trace_clk

Figure 27.  Platform Designer NOC Clocks Sub-window
Level Two Title