Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

5.1.9.3.2. Use Case 2—Configure External PHY RGMII-Internal Delay (RGMII-ID)

The RGMII 2.0 specification introduced the delay on-chip at the source. Devices which support the internal delay features are commonly referred as RGMII-ID. The Agilex™ 3 EMAC does not support RGMII-ID, but today most of the PHY do support RGMII 2.0.

The RGMII-ID provides you with a convenient way to configure PHY specific RX/TX clock delay register which can be used to adjust the timing of the clock signals to account for signal skew.

When selecting a PHY device, consider the desired Ethernet rate, available I/O and transceivers, PHY devices that offer the RGMII-ID skew control feature, and device driver availability.