Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

12.2.6.9. Resets Circuitry

The MPFE takes in four primary reset inputs; f2sdram_axi_reset, l3_rst_n, emif_rst_n, and the cs_at_rst_n.

Additional details on MPFE resets are available in the Reset Manager chapter.

The connectivity between the reset manager and the MPFE is shown in the following diagram.

Figure 296. Reset Manager MPFE Connectivity
Table 363.  Reset Signal Descriptions
Reset Description

f2sdram_axi_reset

Resets either side of the FPGA-to-SDRAM asynchronous bridge.

l3_rst_n

Resets the MPFE TBU and the MPFE NOC ports that interface to the CCU/NCORE and MPFE TBU.

emif_rst_n

Resets the IOBank facing ports and the EMIF in the MPFE.

cs_at_rst_n

Resets the trace observer.