Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

7.6.4. MPFE Clock Group

The following diagram shows the MPFE clock group.

Figure 259. MPFE Clock Group Block Diagram

The following table shows the clock information for the MPFE clock group.

Table 300.  MPFE Clock Group Signals
Clock Group Clock Name Source Destination Description
MPFE mpfe_clk IOBank0 MPFE Clock provided by IOBank0 for MPFE NoC, TBU, and the MPFE facing portion of the F2SDRAM bridge.
mpfe_p1_clk IOBank0 MPFE Clock provided by IOBank0 for the IOBank0_P1 target NIU.
mpfe_csr_clk IOBank0 MPFE Clock provided by IOBank0 CSR port for the IOBank0_CSR target NIUs in MPFE.
f2h_clk Fabric APS F2H bridge clock from fabric
f2sdram_clk Fabric MPFE F2SDRAM bridge clock from fabric