Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

4.3.6.4.1. Interrupt Interfaces for TBU

Each TBU includes an interrupt interface that provides global, per-context, and performance interrupts.

Table 99.  TBU Interrupt signal connection

Signal Name

IO

Connectivity

Description

ras_irpt

O

Connected to GIC

RAS Interrupt

pmu_irpt

O

Connected to GIC

PMU Interrupt