Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

15.5.1. Debug APB

The debug APB is a network of debug and trace peripherals interconnected via the AMBA peripheral bus (APB) and allows a debugger to gain access to debug and trace system for auto-detection and configuration, as well as to offload trace data from the embedded trace FIFOs.

The diagram below shows the debug APB bus connectivity highlighted in orange color, and the debug access port (DAP) and APB-related IP blocks (Serial Wire JTAG-Debug Port (SWJ-DP), AMBA peripheral bus-access port (APB-AP), AXI-access port (AXI-AP), AMBA peripheral bus-interconnect (APB-IC’s), and ROM tables) highlighted in orange color.

Note: The diagram does not show the underlying explicit details of the APB interconnect which could differ due to partitioning and clock domains.
Figure 323. Block Diagram of Debug APB Network

The first section is made up of the SWJ-DP, 1x3 APB-IC, Main ROM table, APB-AP, and AXI-AP. This section is the CoreSight* debug access port (DAP).

The DAP connects to the second APB-IC which includes connections to the debug peripheral ROM table, CoreSight* debug and trace system, and to the FPGA 1x2 APB-IC.

An APB interconnect provides connections from a debugger, connected through the CoreSight* debug access port (DAP) or an on-chip debug agent connected via the PSS NoC, to the CoreSight* debug and trace system.