Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

12.2.6.10. Clocks Circuitry

The IOBank provides a clock output for each of its initiator NIU ports that is to be used to clock the associated target NIU in the MPFE, so that the two associated NIUs run asynchronously with each other. The Port 0 clock (32-bit controller) from IOBank_0 is also used as the MPFE_clk. The MPFE_clk is to be treated as being asynchronous to the other NIU clocks.

Additional details on MPFE clocks are available in the Clock Manager chapter.

The following diagram shows the clock connectivity for the MPFE.

Figure 297. Clock Connectivity for the MPFE
Table 364.  Clock Description
Clock Description

mpfe_clk

Clock provided by IOBank0 for MPFE NoC, TBU, and the MPFE facing portion of the FPGA-to-SDRAM Bridge. Derived from IOBank Port 0 clock.

mpfe_p1_clk

Clock provided by IOBank0 for the IOBank0_P1 target NIU

mpfe_csr_clk

Clock provided by IOBank0 CSR port for the IOBank0_CSR target NIUs in MPFE.

f2sdram_axi_clock

Clock for the fabric facing portion of the FPGA-to-SDRAM.

fpga2hps_clock

Clock for the fabric facing portion of the FPGA-to-HPS.