Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

12.3.2.5.1. Calculating Latency

The following sequence of operations are needed to collect the latency numbers from 1G/2.5G/5G/10G Multirate Ethernet PHY IP and update these values into EMAC latency registers. All 1G/2.5G/5G/10G Multirate Ethernet PHY addresses mentioned in the steps below are word addresses. You must convert the incoming byte aligned address to word aligned address before feeding them into 1G/2.5G/5G/10G Multirate Ethernet PHY control and status register (CSR).
  1. Read the TX/RX DL values from the DL soft registers 0x19:0x18 (1G/2.5G/5G/10G Multirate Ethernet PHY) and 0x1B:0X1A (1G/2.5G/5G/10G Multirate Ethernet PHY) respectively and calculate the TX/RX latency based on the equations shown in the Latency Calculation for 10M/100M/1G/2.5G table. Check the validity of the data through the 0x17 (MR PHY) [0/1]th bit before reading the DL values.
  2. Observe that the soft PCS delays are calculated and updated in the registers from 0x1C to 0x1F (1G/2.5G/5G/10G Multirate Ethernet PHY), which must be added to the DL latencies calculated in step 1.
  3. Convert the TX and RX latency to 16 bits nanosecond and 16 bits fractional nanosecond format by multiplying them by 2^16 or 65536.
  4. Add the TX/RX PMA delay in nanosecond and fractional nanosecond formats to the result.
  5. Program the calculated values above into the XGMAC Ingress/Egress correction registers.
    1. Program the upper 16-bit TX values to the XGMAC register 0xD60 (this is the TX ns value) [15:0] bits and 0s to [31:16] bits as these are 32-bit registers.
    2. Program the [15:8] (from lower 16-bit) TX values to the XGMAC register 0xD64 (this is the TX fns value) [15:8] bits as these are 32-bit registers.
    3. Program the upper 16-bit RX values to XGMAC register 0xD58 (this is the RX ns value) [15:0] bits and 0s to the [31:16] bits since these are 32-bit registers.
    4. Program the [15:8] (from lower 16-bit) RX values to the XGMAC register 0xD5C (this is the RX fns value) [15:8] bits since these are 32-bit registers.
These delays might vary with each power-up of the board due to different bit slips and slightly different FIFO fill levels. This variation occurs in the path from the AIB crossing to the transceiver interface, even when settings are unchanged. Altera recommends that you measure each time after power up and get these results through the CSR accesses, even though the simulation results show the same latency numbers. In the DR flow, the latency values change after the speed change.