Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

ID 848530
Date 6/23/2025
Public
Document Table of Contents

3.6.3.2.4. Cache Data RAM Latency

The L3 data RAM interface is implemented with the following latency on the input and output paths:
  • 1-cycle write latency on the input path to the L3 data RAMs.
  • 2-cycle ready latency on the output path from the L3 data RAMs.
Figure 7. L3 Data RAM Timing